Systolic Array Implementation of DFT with Reduced Multipliers Using Triple Matrix Product

Abstract

A generic 2D systolic array for N point Discrete Fourier Transform using triple matrix product algorithm is proposed. The array can be used for a non power of two sized N point DFT where N=N₁N₂ is a composite number. It uses an array of size N₂×(N₁+1) which requires(2N+4N₂) multipliers. For a DFT of size 4N₂ (i.e multiple of four), an optimized design which requires 4N₂ number of multipliers is proposed. It is observed that the proposed optimized structure reduces the number of multipliers by 66.6% as compared to the generic array structure while maintaining the same time complexity. Two examples are illustrated, one with non power of two size DFT and another with a DFT of size 4N₂. Both the generic and optimized structures use the triple matrix product representation of DFT. The two structures are synthesized using Xilinx ISE 11.1 using the target device as xc5vtx240t-2ff1759 Virtex-5 FPGA. The proposed structure produces unscrambled stream of DFT sequence at output avoiding a necessity of reordering buffer. The array can be used for matrix -matrix multiplication and to compute the diagonal elements of a triple-matrix multiplication.