Millisecond-Range Liquid-Phase Processing of Silicon-Based Hetero-nanostructures

Abstract

The downscaling and stressor technology of Si based devices is extending the performance of the silicon channel to its limits. Further downsizing of CMOS devices below 16 nm will need to solve some of the practical limits caused by one of the integration issues, such as chip performance, cost of development and production, power dissipation, reliability, etc. One solution for the performance progress which can overcome the downsizing limit in silicon technology is the integration of different functional optoelectronic elements within one chip.

We have realized a compact, CMOS compatible and fully integrated solution for the integration of III–V compound semiconductors with silicon technology for optoelectronic applications. The III–V nanostructured semiconductors are synthesized in either silicon or SOI wafers using the combined ion implantation and millisecond flash lamp annealing (FLA) techniques (Prucnal et al. in Nano Lett. 11:2814, 2011). The FLA appears to be the most suitable one for this purpose. The energy budget introduced to the sample during FLA is sufficient to recrystallize silicon amorphized during implantation and to form III–V nanocrystals (NCs). In this paper we will present research results of the microstructural, optical and electrical properties of III–V quantum dots (InAs, GaAs and InP) formed in silicon and on SOI wafers. The influence of the annealing conditions and the lattice mismatch between III–V semiconductors and silicon on the shape of the III–V quantum dots will be examined. The annealing is performed at temperatures by far exceeding the melting point of bulk compound semiconductors, which leads to the formation of III–V nanostructures due to liquid phase epitaxy and enhances the probability for the incorporation of silicon atoms into III–V NCs. Silicon atoms are commonly used as n-type dopants in most III–V semiconductors. Therefore, liquid phase processing leads to the formation of heavily n-type doped single crystalline III–V nanostructures on silicon. If we consider that the synthesized NCs are n-type, by using a p-type silicon substrate a heterojunction can be formed between the III–V NCs and p-type Si. Conventional selective etching has been used to form the n-III–V/p-Si heterojunction. Current-voltage measurements confirm the heterojunction diode formation between n-type III–V quantum dots and p-type Si. The main advantage of our method is its ability to be integrated into large-scale silicon technology, which also allows applying it to Si-based optoelectronic devices.