Abstract
Low power consumption or high execution speed is achieved by making an application specific design. However, today’s systems also require flexibility in order to allow running similar or updated applications (e.g. due to changing standards). Finding a good trade-off between reconfigurability and performance is a challenge.This work presents a design methodology to generate application-domain specific heterogeneous coarse-grain reconfigurable architectures. The specification of the reconfigurable architecture is given by a set of example applications which define the whole range of its required functionality. These applications are analyzed to extract common building blocks, which can be reused between them.In the next step, the circuits of the application are merged to a single reconfigurable module. The major part of this work describes the according tool and its algorithm. Its main task is to optimize the interconnect by hierarchically grouping the functional units. Additional resources can be added to enable future applications. The tool generates the HDL source for a module with the instances of all blocks and the reconfigurable interconnect.The feasibility of the methodology is demonstrated by the design of reconfigurable architectures for digital filters as well as simple logic networks.
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Notes
- 1.
A left-recursive acronym for “Yosys Open Synthesis Suite”.
- 2.
VHDL support is in development as of this writing.
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Acknowledgements
This work has been supported (in part) by the Austrian COMET K-project ECV under contract no. 815105.
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Glaser, J., Wolf, C. (2014). Methodology and Example-Driven Interconnect Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable Architectures. In: Haase, J. (eds) Models, Methods, and Tools for Complex Chip Design. Lecture Notes in Electrical Engineering, vol 265. Springer, Cham. https://doi.org/10.1007/978-3-319-01418-0_12
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