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SRISC: Open Source Soft Processor Side Channel Analysis Attack Framework Using RISC-V

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Asia Pacific Advanced Network (APANConf 2023)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 1995))

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Abstract

Side channel analysis (SCA) attacks on soft processor systems (such as RISC-V and LEON3) are typically performed on FPGA prototyping boards. For the first time, this paper presents a RISC-V-based soft processor SCA framework (referred to as SRISC) to perform power-based, electromagnetic radiation-based and execution time-based SCA attacks against cryptographic algorithms and to test countermeasures on soft processor systems. The proposed SRISC framework is demonstrated on a commercial side-channel analysis attack board, SASEBO-GIII (referred to as SRISC-SASEBO). SRISC consists of hardware modules to calculate cryptographic operations using hardware circuits.

As a case study to test the implementation of a countermeasure, a balanced AES countermeasure is discussed to show the effectiveness of building hybrid countermeasures (which use both hardware and software components–hardware/software co-design) to reduce the information leakage to mitigate power analysis attacks. The software implementation of the balanced AES countermeasure revealed 14 bytes (of 16 bytes) of the secret key in 18,000 encryptions. The balanced hybrid AES countermeasure revealed only eight bytes (of 16 bytes) of the secret key for the same number of encryptions making software-hardware co-design countermeasures more promising to mitigate power analysis attack vulnerabilities.

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Authors and Affiliations

  1. School of Electrical and Computer Engineering, The University of Sydney, Sydney, NSW, 2006, Australia

    Darshana Jayasinghe & Sri Parameswaran

Authors
  1. Darshana Jayasinghe
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  2. Sri Parameswaran
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Corresponding author

Correspondence to Darshana Jayasinghe .

Editor information

Editors and Affiliations

  1. University of Peradeniya, Peradeniya, Sri Lanka

    Damayanthi Herath

  2. Osaka University, Suita, Osaka, Japan

    Susumu Date

  3. University of Peradeniya, Peradeniya, Sri Lanka

    Upul Jayasinghe

  4. Pennsylvania State University, University Park, PA, USA

    Vijaykrishnan Narayanan

  5. University of Peradeniya, Peradeniya, Sri Lanka

    Roshan Ragel

  6. Tsinghua University, Beijing, China

    Jilong Wang

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Jayasinghe, D., Parameswaran, S. (2024). SRISC: Open Source Soft Processor Side Channel Analysis Attack Framework Using RISC-V. In: Herath, D., Date, S., Jayasinghe, U., Narayanan, V., Ragel, R., Wang, J. (eds) Asia Pacific Advanced Network. APANConf 2023. Communications in Computer and Information Science, vol 1995. Springer, Cham. https://doi.org/10.1007/978-3-031-51135-6_10

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  • DOI: https://doi.org/10.1007/978-3-031-51135-6_10

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-031-51134-9

  • Online ISBN: 978-3-031-51135-6

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