Abstract
The Advanced Microcontroller Bus Architecture (AMBA) is an open System-on-Chip bus protocol for high performance buses to communicate with low-power devices. In the AMBA Advanced High-performance Bus (AHB), a system bus is used to connect a processor, direct memory access (DMA), and high-performance memory controllers. The AMBA Advanced Peripheral Bus (APB) is used to connect UART (Universal Asynchronous Receiver Transmitter). It also contains a bridge, which connects the AHB and APB buses. Bridges are standard bus-to-bus interfaces that allow Interface Protocols connected to different buses to communicate with each other in a standardized way. In this work, we have done an interface between the AHB and SRAM which performs read and write operation. The AHB SRAM Controller provides a standard AHB interface to translate AHB bus reads and writes into reads and writes with the signaling and timing of a standard 32-bit synchronous SRAM. The design has been simulated in EDA Playground with Riviera-pro tool and EPWave to display the output.
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Mallikarjunaswamy, M.S., Dambal, J., Kuthethure, A., Ashwini, G., Sumanth, K. (2024). Design of Advanced High-Performance Bus Master to Access a SRAM Block. In: Aurelia, S., J., C., Immanuel, A., Mani, J., Padmanabha, V. (eds) Computational Sciences and Sustainable Technologies. ICCSST 2023. Communications in Computer and Information Science, vol 1973. Springer, Cham. https://doi.org/10.1007/978-3-031-50993-3_33
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DOI: https://doi.org/10.1007/978-3-031-50993-3_33
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