Abstract
Through Silicon Via (TSV) is a technique used in three-dimensional (3D) integrated circuit (IC) packaging to vertically stack layers for the purpose of establishing electrical and mechanical connections. Nevertheless, TSV faces certain challenges that pose risks to its reliability, many of them originated from void formation. Despite its importance, considering the challenges for experimental analysis of the phenomenon, there are a lot of uncertainties about the mechanism of void nucleation. An important parameter affecting void nucleation under stress is the grain type and orientation. This study aims to understand this effect through a systematical analysis, using molecular dynamics simulations. Void formation during tension in the tilt grain boundary and within the grain of a face-centered cubic (FCC) Cu bicrystal is examined. Three misorientation axes— < 100> , < 110> , and < 111 >—with various tilt angles are explored. This study suggests that the level of strain that leads to void nucleation depends on the dislocation network that exists at the grain boundary. Dislocation evolutions throughout loading are examined to define the mechanism of void formation.
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Acknowledgements
The support for this research was made possible through the SoE 2022 Faculty Research Excellence Grant from Santa Clara University. Computing resources were provided by the Wiegand Advanced Visualization Environment (WAVE) at Santa Clara University.
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Shashaani, A., Sepehrband, P. (2024). Void Nucleation in a Through Silicon Via (TSV): Unraveling the Role of Tilt Grain Boundaries Through Atomistic Investigation. In: TMS 2024 153rd Annual Meeting & Exhibition Supplemental Proceedings. TMS 2024. The Minerals, Metals & Materials Series. Springer, Cham. https://doi.org/10.1007/978-3-031-50349-8_87
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