Abstract
A digital delay generator can have a wide range and high resolution if divided into coarse and fine parts. In this paper, the implementation of a delay generator using counters and delay chains is presented using Field Programmable Gate Array (FPGA). The main contribution of the proposal is the implementation of delay chains with behavioral descriptions, applying a method to linearize them with no manual editing of the layout or routing, based on timing analysis. The building blocks consist of the digitally-controlled delay line (DCDL), employed for fine-tuning, a state machine for coarse-tuning, and the time-to-digital converter (TDC) to correct the error due to the unknown time interval between input and clock. The system is implemented on a Cyclone V SoC 5CSXFC6C6U23C8 device, with a 10-bit delay generator, achieving around 625 ps resolution in the LSB, and a range of 170 ns. The values measured of INL are [−0.22, 1.91] in LSB.
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Acknowledgment
This work is supported by Foundation for Research Support of Mato Grosso (FAPEMAT) and National Council for Scientific and Technological Development (CNPq).
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Oliveira, V.J.S., Santos, E.F., Cajado, W.R., Schmatz, F.H., Melo, W.R. (2023). A Digitally Controlled Delay Generator Implemented with Cyclone V FPGA Using Timing Analysis. In: Iano, Y., Saotome, O., Kemper Vásquez, G.L., de Moraes Gomes Rosa, M.T., Arthur, R., Gomes de Oliveira, G. (eds) Proceedings of the 8th Brazilian Technology Symposium (BTSym’22). BTSym 2022. Smart Innovation, Systems and Technologies, vol 353. Springer, Cham. https://doi.org/10.1007/978-3-031-31007-2_4
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DOI: https://doi.org/10.1007/978-3-031-31007-2_4
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