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A Survey of On-Chip Hybrid Interconnect for Multicore Architectures

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Context-Aware Systems and Applications (ICCASA 2022)

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Abstract

In this paper, we present a survey of hybrid interconnects for multicore architecture proposed in the literature. Before making a survey, we introduce an overview of on-chip hybrid interconnects and the taxonomies to classify them. We also present different architectures of standard interconnects that are frequently used for multi/many-core system in both the academia and industry. Finally, we conduct a survey of hybrid interconnects where we categorize them into two different groups. The first one includes hybrid interconnects that create the interconnects by using different Network-on-Chip topologies. We named this group as topology-mixture hybrid interconnect. The second group, named architecture-mixture hybrid interconnects, combines different architectures, such as bus and NoC, to form hybrid interconnects.

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Notes

  1. 1.

    A node is any part that joins the network like a PE or a buffer.

References

  1. Avakian, A., et al.: A reconfigurable architecture for multicore systems. In: IPDPSW, pp. 1–8 (2010). https://doi.org/10.1109/IPDPSW.2010.5470753

  2. Balfour, J., Dally, W.J.: Design tradeoffs for tiled CMP on-chip networks. In: Proceedings of the 20th Annual International Conference on Supercomputing, ICS 2006, pp. 187–198. ACM, New York (2006). https://doi.org/10.1145/1183401.1183430. http://doi.acm.org/10.1145/1183401.1183430

  3. Balkan, A., Qu, G., Vishkin, U.: A mesh-of-trees interconnection network for single-chip parallel processing. In: International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2006, pp. 73–80 (2006). https://doi.org/10.1109/ASAP.2006.6

  4. Balkan, A.O., Qu, G., Vishkin, U.: An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing. In: Proceedings of the 45th Annual Design Automation Conference, DAC 2008, pp. 435–440, ACM, New York (2008). https://doi.org/10.1145/1391469.1391583. http://doi.acm.org/10.1145/1391469.1391583

  5. Bourduas, S., Zilic, Z.: Modeling and evaluation of ring-based interconnects for network-on-chip. J. Syst. Archit. 57(1), 39–60 (2011). https://doi.org/10.1016/j.sysarc.2010.07.002. http://www.sciencedirect.com/science/article/pii/S138376211000069X. Special Issue On-Chip Parallel and Network-Based Systems

  6. Camacho, J., Flich, J., Roca, A., Duato, J.: PC-mesh: a dynamic parallel concentrated mesh. In: 2011 International Conference on Parallel Processing (ICPP), pp. 642–651 (2011). https://doi.org/10.1109/ICPP.2011.21

  7. Das, R., et al.: Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs. In: HPCA 2009, pp. 175–186 (2009). https://doi.org/10.1109/HPCA.2009.4798252

  8. Duato, J., Yalamanchili, S., Lionel, N.: Interconnection Networks: An Engineering Approach. Morgan Kaufmann Publishers Inc., San Francisco (2002)

    Google Scholar 

  9. El-Rewini, H., Abd-El-Barr, M.: Advanced Computer Architecture and Parallel Processing (Wiley Series on Parallel and Distributed Computing). Wiley-Interscience (2005)

    Google Scholar 

  10. Gazettabyte: Altera’s 30 billion transistor FPGA (2016). http://www.gazettabyte.com/home/2015/6/28/alteras-30-billion-transistor-fpga.html

  11. Gebali, F.: Interconnection Networks, pp. 83–103. Wiley (2011). https://doi.org/10.1002/9780470932025.ch5

  12. Giefers, H., Platzner, M.: A triple hybrid interconnect for many-cores: reconfigurable mesh, NoC and barrier. In: FPL, pp. 223–228 (2010). https://doi.org/10.1109/FPL.2010.52

  13. Grama, A., Gupta, A., Karypis, G., Kumar, V.: Introduction to Parallel Computing, 2nd edn. Addison-Wesley Longman Publishing Co., Inc., Boston (2002)

    MATH  Google Scholar 

  14. Grasset, A., et al.: The Morpheus heterogeneous dynamically reconfigurable platform. Int. J. Parallel Program. 39(3), 328–356 (2011)

    Article  Google Scholar 

  15. Grot, B., et al.: Express cube topologies for on-chip interconnects. In: HPCA, pp. 163–174 (2009). https://doi.org/10.1109/HPCA.2009.4798251

  16. Guerrier, P., Greiner, A.: A generic architecture for on-chip packet-switched interconnections. In: DATE, pp. 250–256 (2000). https://doi.org/10.1109/DATE.2000.840047

  17. Hur, J.: Customizing and hardwiring on-chip interconnects in FPGAs. Ph.D. thesis, Delft University of Technology, Delft, Netherlands (2011)

    Google Scholar 

  18. Jerger, N.E., Peh, L.S.: On-Chip Networks, 1st edn. Morgan and Claypool Publishers (2009)

    Google Scholar 

  19. Jin, Y., et al.: Communication-aware globally-coordinated on-chip networks. Parallel Distrib. Syst. 23(2), 242–254 (2012). https://doi.org/10.1109/TPDS.2011.164

    Article  Google Scholar 

  20. Kang, K., Park, S., Lee, J.B., Benini, L., Micheli, G.D.: A power-efficient 3-D on-chip interconnect for multi-core accelerators with stacked L2 cache. In: 2016 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 1465–1468 (2016)

    Google Scholar 

  21. Kim, J., Balfour, J., Dally, W.: Flattened butterfly topology for on-chip networks. Comput. Archit. Lett. 6(2), 37–40 (2007). https://doi.org/10.1109/L-CA.2007.10

    Article  Google Scholar 

  22. Kim, W.J., Hwang, S.Y.: Design of an area-efficient and low-power NoC architecture using a hybrid network topology. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. E91-A(11), 3297–3303 (2008). https://doi.org/10.1093/ietfec/e91-a.11.3297

  23. Kogel, T., Leupers, R., Meyr, H.: Classification of platform elements. In: Kogel, T., Leupers, R., Meyr, H. (eds.) Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms, pp. 15–32. Springer, Dordrecht (2006). https://doi.org/10.1007/1-4020-4826-2_3

    Chapter  MATH  Google Scholar 

  24. Kumar, R., et al.: Heterogeneous chip multiprocessors. Computer 38(11), 32–38 (2005)

    Article  Google Scholar 

  25. Manevich, R., et al.: Best of both worlds: a bus enhanced NoC (BENoC). In: Networks-on-Chip, pp. 173–182 (2009). https://doi.org/10.1109/NOCS.2009.5071465

  26. Matos, D., Concatto, C., Carro, L.: Reconfigurable intercommunication infrastructure: NoCs. In: Beck, A.C.S., Lang Lisbôa, C.A., Carro, L. (eds.) Adaptable Embedded Systems, pp. 119–161. Springer, New York (2013). https://doi.org/10.1007/978-1-4614-1746-0_5

    Chapter  Google Scholar 

  27. Modarressi, M., Tavakkol, A., Sarbazi-Azad, H.: Virtual point-to-point connections for NoCs. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 29(6), 855–868 (2010). https://doi.org/10.1109/TCAD.2010.2048402

    Article  Google Scholar 

  28. Murali, S., et al.: Designing application-specific networks on chips with floorplan information. In: Proceedings of the 2006 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2006, pp. 355–362. ACM, New York (2006). https://doi.org/10.1145/1233501.1233573. http://doi.acm.org/10.1145/1233501.1233573

  29. Pasricha, S., Dutt, N.: Basic concepts of bus-based communication architectures, chapter 2. In: Pasricha, S., Dutt, N. (eds.) On-Chip Communication Architectures, pp. 17–41. Systems on Silicon, Morgan Kaufmann (2008). https://doi.org/10.1016/B978-0-12-373892-9.00002-5. http://www.sciencedirect.com/science/article/pii/B9780123738929000025

  30. Pham, D., Holt, J., Deshpande, S.: Embedded multicore systems: design challenges and opportunities. In: Hübner, M., Becker, J. (eds.) Multiprocessor System-on-Chip, pp. 197–222. Springer, New York (2011). https://doi.org/10.1007/978-1-4419-6460-1_9

    Chapter  Google Scholar 

  31. Richardson, T., et al.: A hybrid SoC interconnect with dynamic TDMA-based transaction-less buses and on-chip networks. In: VLSI Design, p. 8 (2006). https://doi.org/10.1109/VLSID.2006.10

  32. Rutzig, M., et al.: Multicore platforms: processors, communication and memories. In: Beck, A., Lang Lisbôa, C., Carro, L. (eds.) Adaptable Embedded Systems, pp. 243–277. Springer, Heidelberg (2013). https://doi.org/10.1007/978-1-4614-1746-0_8

    Chapter  Google Scholar 

  33. Sanchez, D., et al.: An analysis of on-chip interconnection networks for large-scale chip multiprocessors. ACM Trans. Archit. Code Optim. 7(1), 4:1–4:28 (2010)

    Google Scholar 

  34. Stensgaard, M., Sparso, J.: ReNoC: a network-on-chip architecture with reconfigurable topology. In: Second ACM/IEEE International Symposium on Networks-on-Chip, 2008, NoCS 2008, pp. 55–64 (2008). https://doi.org/10.1109/NOCS.2008.4492725

  35. Swaminathan, K., Gopi, S., Rajkumar, Lakshminarayanan, G., Ko, S.B.: A novel hybrid topology for network on chip. In: 2014 IEEE 27th Canadian Conference on Electrical and Computer Engineering (CCECE), pp. 1–6 (2014). https://doi.org/10.1109/CCECE.2014.6901083

  36. Todorov, V., Mueller-Gritschneder, D., Reinig, H., Schlichtmann, U., et al.: Deterministic synthesis of hybrid application-specific network-on-chip topologies. Comput.-Aided Des. Integr. Circuits Syst. 33(10), 1503–1516 (2014). https://doi.org/10.1109/TCAD.2014.2331556

    Article  Google Scholar 

  37. Tsai, K.L., et al.: Design of low latency on-chip communication based on hybrid NoC architecture. In: NEWCAS, pp. 257–260 (2010). https://doi.org/10.1109/NEWCAS.2010.5603934

  38. Wang, C., Hu, W.H., Lee, S.E., Bagherzadeh, N.: Area and power-efficient innovative congestion-aware network-on-chip architecture. J. Syst. Archit. 57(1), 24–38 (2011). https://doi.org/10.1016/j.sysarc.2010.10.009. http://www.sciencedirect.com/science/article/pii/S1383762110001359. Special Issue On-Chip Parallel And Network-Based Systems

  39. Yin, J., Zhou, P., Sapatnekar, S.S., Zhai, A.: Energy-efficient time-division multiplexed hybrid-switched NoC for heterogeneous multicore systems. In: Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium, IPDPS 2014, Washington, DC, USA, pp. 293–303. IEEE Computer Society (2014). https://doi.org/10.1109/IPDPS.2014.40

  40. Zarkesh-Ha, P., et al.: Hybrid network on chip (HNoC): local buses with a global mesh architecture. In: System Level Interconnect Prediction, pp. 9–14. ACM, New York (2010)

    Google Scholar 

  41. Zhao, H., et al.: A hybrid NoC design for cache coherence optimization for chip multiprocessors. In: DAC, pp. 834–842. ACM, New York (2012)

    Google Scholar 

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Acknowledgment

We acknowledge Ho Chi Minh City University of Technology (HCMUT), VNU-HCM for supporting this study.

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Authors and Affiliations

  1. Ho Chi Minh City University of Technology (HCMUT), 268 Ly Thuong Kiet Street, District 10, Ho Chi Minh City, Vietnam

    Cuong Pham-Quoc

  2. Vietnam National University - Ho Chi Minh City (VNU-HCM), Ho Chi Minh City, Vietnam

    Cuong Pham-Quoc

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  1. Cuong Pham-Quoc
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Correspondence to Cuong Pham-Quoc .

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Editors and Affiliations

  1. Nguyen Tat Thanh University, Ho Chi Minh City, Vietnam

    Cong Vinh Phan

  2. Mekong University, Vinh Long Province, Vietnam

    Thanh Dung Nguyen

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Pham-Quoc, C. (2023). A Survey of On-Chip Hybrid Interconnect for Multicore Architectures. In: Phan, C.V., Nguyen, T.D. (eds) Context-Aware Systems and Applications. ICCASA 2022. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 475. Springer, Cham. https://doi.org/10.1007/978-3-031-28816-6_5

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  • DOI: https://doi.org/10.1007/978-3-031-28816-6_5

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