Abstract
The architecture of a computer can be efficiently designed, by synchronizing the major sections of a computer namely the Central Processing Unit (CPU), memory, data path, pipeline structure, Arithmetic, and Logic Unit (ALU). The data storage and organization depend on the memory allotment and specific memory design carried out in accordance with the CPU specifications. A specific memory hierarchy is followed for the CPU, which starts with the units near the processor such as memory registers, cache memory, main memory, secondary memory, and finally the flash storage devices. This hierarchy is based on parameters like speed, response time, program complexity, and overall storage capacity for the computer. This work focuses on the cache memory which is a high-speed special memory, essential in the memory section of computer architecture. A modified version of the vector triad benchmark program is run on four computer systems with different specifications to check the performance and understand the cache levels. The problem size, i.e. the execution of the benchmark program is defined to get iterations and plotting comparison curves for time and throughput analysis for test cases of computers. As the level of cache changes from level 1 to level 3, the throughput curve decreases. Also, when more processes are active, while the benchmark code is running, then a significant rise in computation time, data access time, and total time values are observed which reflects on the computer performance.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Asadi, G.H., Sridharan, V., Tahoori, M.B., Kaeli, D.: Balancing performance and reliability in the memory hierarchy. In: IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2005, pp. 269–279. IEEE (2005)
Faris, S.: How important is a processor cache?. https://smallbusiness.chron.com/important-processor-cache-69692.html. Accessed 11 Apr 2021
Kumar, S., Singh, P.: An overview of modern cache memory and performance analysis of replacement policies. In: 2016 IEEE International Conference on Engineering and Technology (ICETECH), pp. 210–214. IEEE (2016)
Rodriguez E, Singh S.: Cache memory. https://www.britannica.com/technology/cache-memory. Accessed 8 Apr 2021
What is response time? - Definition from techopedia. https://www.techopedia.com/definition/9181/response-time. Accessed 6 Apr 2021
Cache memory. https://12myeducation.blogspot.com/2020/02/cache-memory-cach-memory.html. Accessed 11 Apr 2021
Moulik, S., Das, Z.: Tasor: A temperature-aware semi-partitioned real-time scheduler. In: TENCON 2019–2019 IEEE Region 10 Conference (TENCON), pp. 1578–1583. IEEE (2019)
Sharma, Y., Moulik, S., Chakraborty, S.: Restore: real-time task scheduling on a temperature aware finfet based multicore. In: 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 608–611. IEEE (2022)
Moulik, S.: Reset: a real-time scheduler for energy and temperature aware heterogeneous multi-core systems. Integration 77, 59–69 (2021)
Moulik, S., Das, Z., Saikia, G.: Ceat: a cluster based energy aware scheduler for real-time heterogeneous systems. In: 2020 IEEE International Conference on Systems, Man, and Cybernetics (SMC), pp. 1815–1821. IEEE (2020)
Hallnor, E.G., Reinhardt, S.K.: A unified compressed memory hierarchy. In: 11th International Symposium on High-Performance Computer Architecture, pp. 201–212. IEEE (2005)
Microbenchmarking for Architectural Exploration (and more). https://moodle.rrze.uni-erlangen.de/pluginfile.php/15304/mod_resource/content/1/03_Microbenchmarking.pdf. Accessed 14 Apr 2021
Burke J.: What is throughput?. https://www.techtarget.com/searchnetworking/definition/throughput. Accessed 10 Apr 2021
Hager G.: Benchmarking the memory hierarchy of the new AMD Ryzen CPU using the vector triad. https://blogs.fau.de/hager/archives/7810. Accessed 7 Apr 2021
Jain R.: Memory hierarchy design and its characteristics. https://www.geeksforgeeks.org/memory-hierarchy-design-and-its-characteristics/. Accessed 12 Apr 2021
Parhami, B.: Computer Architecture: From Microprocessors to Supercomputers. Oxford University Press, New York (2005)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2023 The Author(s), under exclusive license to Springer Nature Switzerland AG
About this paper
Cite this paper
Mankad, V., Shah, V., Gajjar, S., Shah, D. (2023). Performance Analysis of Cache Memory in CPU. In: Patel, K.K., Santosh, K.C., Patel, A., Ghosh, A. (eds) Soft Computing and Its Engineering Applications. icSoftComp 2022. Communications in Computer and Information Science, vol 1788. Springer, Cham. https://doi.org/10.1007/978-3-031-27609-5_14
Download citation
DOI: https://doi.org/10.1007/978-3-031-27609-5_14
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-031-27608-8
Online ISBN: 978-3-031-27609-5
eBook Packages: Computer ScienceComputer Science (R0)