Designing Low-Power and High-Speed FPGA-Based Binary Decision Tree Hardware Accelerators

Abstract

With the rapid development of Internet-of-Things (IoT) technologies and edge computing, identifying efficient solutions for data mining tasks such as classification is becoming crucial. Binary Decision Trees (DT) are one of the most used classifiers, due to their ability to handle a large amount of data with a high accuracy. More important, inference of DTs is well suited to be accelerated through custom hardware designs that allow enabling parallel and power-efficient computations with respect to the software-based counterpart. This is very important especially in the context of edge computing, where the computation is performed locally to the data acquisition with a reduced hardware-power budget. This paper describes a novel approach to design low-power and high-speed FPGA-based hardware accelerators of DTs. It is based on the idea of a novel hardware processing element, the so-called Super PE, that can be configured to execute in parallel the operation of three nodes belonging to two consecutive levels of the tree: a parent and its two children nodes. When implemented on the FPGA platform hosted on the Xilinx Zynq XC7Z020-1CLG400C heterogeneous System on Chip (SoC), the new design has shown a dynamic power reduction of up to 41%, in comparison with previously published designs based on the conventional PE. Moreover, compared to a pure software-based DT implementation, the proposed hardware accelerator, integrated into a complete embedded system, has shown an execution speed-up of about 21$\times$.