Abstract
With high-level computing facilities starting to become more affordable, there is a notable rise in the use of Graphics Processing Unit (GPU) for applications in general. A GPU is and has always been considered a co-processor and hardware with high cost-performance. It has also been seen that FPGA implementation of encryption is slower than GPGPU implementation. Therefore, the implementation of various cryptographic modules on GPU is becoming more and more popular among researchers. This paper aims to propose and test a fast implementation of AES, and its multiple modes like ECB, CBC, CTR on the latest Turing Architecture based GPUs and compare its performance with its predecessor Pascal Architecture based GPUs. The results gathered from the experiments show that the output comparisons of ECB and CTR mode make it clear that the ability to parallelize directly affects the throughput. The Turing architecture has undoubtedly provided a tremendous amount of hardware acceleration and provided high results on even a medium-range GPU like the 1650.
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References
Burgess, J.: RTX on – the NVIDIA Turing GPU. In: 2019 IEEE Hot Chips 31 Symposium (HCS) (2019). https://doi.org/10.1109/hotchips.2019.8875651
Burgess, J.: RTX on—The NVIDIA Turing GPU. IEEE Micro 40, 36–44 (2020). https://doi.org/10.1109/mm.2020.2971677
Cheong, H.-S., Lee, W.-K.: Fast implementation of block ciphers and PRNGs for Kepler GPU architecture. In: 2015 5th International Conference on IT Convergence and Security (ICITCS) (2015). https://doi.org/10.1109/icitcs.2015.7292982
Barlas, G., Hassan, A., Jundi, Y.A.: An analytical approach to the design of parallel block cipher encryption/decryption: a CPU/GPU case study. In: 2011 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing (2011). https://doi.org/10.1109/pdp.2011.51
Che, S., Boyer, M., Meng, J., Tarjan, D., Sheaffer, J.W., Skadron, K.: A performance study of general-purpose applications on graphics processors using CUDA. J. Parallel Distrib. Comput. 68, 1370–1380 (2008). https://doi.org/10.1016/j.jpdc.2008.05.014
Lee, W.-K., Cheong, H.-S., Phan, R.-W., Goi, B.-M.: Fast implementation of block ciphers and PRNGs in Maxwell GPU architecture. Clust. Comput. 19, 335–347 (2016). https://doi.org/10.1007/s10586-016-0536-2
Nishikawa, N., Iwai, K., Kurokawa, T.: High-performance symmetric block ciphers on CUDA. In: 2011 Second International Conference on Networking and Computing (2011). https://doi.org/10.1109/icnc.2011.40
Le, D., Chang, J., Gou, X., Zhang, A., Lu, C.: Parallel AES algorithm for fast data encryption on GPU. In: 2010 2nd International Conference on Computer Engineering and Technology (2010). https://doi.org/10.1109/iccet.2010.5486259
Abdelrahman, A.A., Dahshan, H., Salama, G.I.: Enhancing the actual throughput of the AES algorithm on the Pascal GPU architecture. In: 2018 3rd International Conference on System Reliability and Safety (ICSRS) (2018). https://doi.org/10.1109/icsrs.2018.8688724
Mei, C., Jiang, H., Jenness, J.: CUDA-based AES parallelization with fine-tuned GPU memory utilization. In: 2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Ph.D. Forum (IPDPSW) (2010). https://doi.org/10.1109/ipdpsw.2010.5470766
Biryukov, A., Großschädl, J.: Cryptanalysis of the full AES using GPU-like special-purpose hardware. Fund. Inform. 114, 221–237 (2012). https://doi.org/10.3233/fi-2012-626
An, S., Seo, S.C.: Highly efficient implementation of block ciphers on graphic processing units for massively large data. Appl. Sci. 10, 3711 (2020). https://doi.org/10.3390/app10113711
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Chugh, G., Saji, S.A., Singh Bhati, N. (2022). Fast Implementation of AES Modes Based on Turing Architecture. In: Sugumaran, V., Upadhyay, D., Sharma, S. (eds) Advancements in Interdisciplinary Research. AIR 2022. Communications in Computer and Information Science, vol 1738. Springer, Cham. https://doi.org/10.1007/978-3-031-23724-9_44
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