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High-Resolution Wide-Bandwidth Time-Interleaved RF ADC

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Multi-Gigahertz Nyquist Analog-to-Digital Converters

Part of the book series: Analog Circuits and Signal Processing ((ACSP))

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Abstract

This chapter delves deep into architectural and circuit capabilities to enable high-resolution ADCs (>10-bits) while preserving the multi-GHz sample rate and bandwidth and maximizing the efficiency. Such high resolution, multi-GHz sample rate and bandwidth, low-power RF sampling ADCs are of great interest in next generation wideband communication, data acquisition, and instrumentation applications. First, the needs and challenges for efficiently realizing such RF sampling ADCs are overviewed, and common ADC architectural choices and their trade-offs are briefly discussed. Consequently, a novel TI hybrid RF sampling ADC is presented, and its performance-enabling principles are detailed. Finally, the experimental verification of the ADC prototype in 28 nm CMOS, including the detailed measurement setup, the measured results, and a comparison with recent state-of-the-art, is treated thoroughly.

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Notes

  1. 1.

    The architectural conception of the proposed three-stage pipelined-SAR sub-ADC took place in the late summer of 2016. This occurred prior to and independent of the first available in open literature work of [88], which was in February 2017.

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Author information

Authors and Affiliations

  1. Stanford University, Stanford, CA, USA

    Athanasios T. Ramkaj

  2. Helmond, Noord-Brabant, The Netherlands

    Marcel J. M. Pelgrom

  3. KU Leuven, Leuven, Belgium

    Michiel S. J. Steyaert & Filip Tavernier

Authors
  1. Athanasios T. Ramkaj
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  2. Marcel J. M. Pelgrom
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  3. Michiel S. J. Steyaert
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  4. Filip Tavernier
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Appendix D: TI ADC Power Estimation with On-Chip Input Buffer

Appendix D: TI ADC Power Estimation with On-Chip Input Buffer

For completeness, we provide here a first-order estimation of the increase in the power consumption, in case an on-chip input buffer would be employed to actively drive this ADC with a sufficiently wide input bandwidth. This estimation assumes a push-pull source follower structure [101] with a low enough output impedance (Z out ≈ 1/g m ≈ 5 Ω). This would necessitate g m,NMOS and g m,PMOS of 100 mS from each of the complementary sides, assuming an equal NMOS/PMOS strength. If we design for a g m/I D of about 10 S/A, easily achievable in process like 28 nm, this would translate to a total quiescent current from the differential circuit of about 20 mA. It is also necessary to utilize a supply voltage of at least 1.8 V to allow a one-row or two-row cascoding for improving the buffer linearity. This would lead to a power consumption from the differential circuit of about 36 mW. If another 4 mW is added for biasing purposes, a total power consumption from the buffer of 40 mW is estimated. This would result in a total ADC plus input buffer power of 198.6 mW, leading to a FoMS and FoMW of 159.5 dB and 58 fJ/conv-step, respectively.

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Ramkaj, A.T., Pelgrom, M.J.M., Steyaert, M.S.J., Tavernier, F. (2023). High-Resolution Wide-Bandwidth Time-Interleaved RF ADC. In: Multi-Gigahertz Nyquist Analog-to-Digital Converters. Analog Circuits and Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-031-22709-7_6

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  • DOI: https://doi.org/10.1007/978-3-031-22709-7_6

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