Abstract
With the advancements of Quantum Computing and its implementing technologies like NMR, IoN trap, the necessity of constructing fault-free quantum circuit is observed. But in way to ensure fault-free circuit, appropriate testing model to be invoked and here in this paper we present an online testing technique that effectively detects control node displacement fault (CNDF) in quantum circuit designed with reversible gates.
Our testing approach involves two steps. In the very first step, the input circuit is transformed to its corresponding testable design by appending additional gates and lines (auxiliary lines). Next, appropriate test vectors are generated and subsequently are applied to find possible node displacement faults in the circuit. The proposed online testing approach is suitable for all type of quantum circuits built with reversible gates (MCT gates). More interestingly, some small changes in the design turn this scheme very effective for ESOP based representation as well. We have extensively tested our approach over a large spectrum of benchmarks and comparison with existing testing algorithms is also summarized in the result tables.
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References
Bhattacharjee, A., Bandyopadhyay, C., Niemann, P., Mondal, B., Drechsler, R., Rahaman, H.: An improved heuristic technique for nearest neighbor realization of quantum circuits in 2D architecture. Integration 76, 40–54 (2021)
Niemann, P., Bandyopadhyay, C., Drechsler, R.: February. Combining SWAPs and remote toffoli gates in the mapping to IBM QX architectures. In 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 200–205. IEEE (2021)
Shor, P.W.: Algorithms for quantum computation: discrete logarithms and factoring. In Foundations of Computer Science, pp. 124–134 (1994)
Grover, L.K.: A fast quantum mechanical algorithm for database search. In Theory of Computing, pp. 212–219 (1996)
Haffner, H., et al.: Scalable multiparticle entanglement of trapped ions. Nature 438, 643–646 (2005)
Laforest, M., et al.: Using error correction to determine the noise model. Phys. Rev. A 75, 133–137 (2007)
Ghosh, J., et al.: High-fidelity CZ gate for resonator based superconducting quantum computers. Phys. Rev. A 87, 022309 (2013)
Veldhorst, M., et al.: A two qubit logic gate in silicon. Nature 526, 410–414 (2015)
Kane, B.: A silicon-based nuclear spin quantum computer. Nature 393, 133–137 (1998)
Fazel, K., Thornton, M., Rice, J., E.: ESOP-based Toffoli gate cascade generation. In IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, pp. 206–209. Citeseer (2007)
Wille, R., Drechsler, R.: BDD-based synthesis of reversible logic for large functions. In DAC 2009, 270–275 (2009)
Gupta, P.A., Agrawal, A., Jha, N.K.: An algorithm for synthesis of reversible logic circuits. IBM Res. Develop. 25(11), 2317–2329 (2006)
Hayes, J.P., Polian, I., Becker, B.: Testing for missing-gate faults in reversible circuits. In IEEE Asian Test Symposium, pp. 100–105 (2004)
Perkowski, M., Biamonte, J., Lukac, M.: Test generation and fault localization for quantum circuits. In International Symposium on Multi-Valued Logic, pp. 62–68 (2005)
Patel, K.N., Hayes, J.P., Markov, I.L.: Fault testing for reversible circuits. In IEEE VLSI Test Symposium, pp. 410–416 (2003)
Kole, D.K., Rahaman, H., Das, D.K., Bhattacharya, B.B.: Derivation of optimal test set for detection of multiple missing-gate faults in reversible circuits. In IEEE Asian Test Symposium, pp.33–38 (2010)
Zamani, M., Tahoori, M.B., Chakrabarty, K.: Ping-pong test: Compact test vector generation for reversible circuits. In IEEE VLSI Test Symposium, pp. 164–169 (2012)
Ramasamy, K., Tagare, R., Perkins, E., Perkowski, M.: Fault localization in reversible circuits is easier than for classical circuits. In IEEE Asian Test Symposium (2004)
Mondal, B., Kole, D.K., Das, D.K., Rahaman, H.: Generator for Test Set Construction of SMGF in Reversible Circuit by Boolean Difference method. In IEEE 23rd Asian Test Symposium, pp. 68–73 (2014)
Rahaman, H., Kole, D.K., Das, D.K., Bhattacharya, B.B.: Fault diagnosis in reversible circuits under missing-gate fault model. Comput. Electr. Eng. 37(4), 475–485 (2011)
Mahammad, S.N., Hari, S.K., Shroff, S., Kamakoti, V.: Constructing online testable circuits using reversible logic. In International Symposium on VLSI Design and Test, pp. 373–383 (2006)
Vasudevan, D.P., Lala, P.K., Jia, D., Parkerson, J.P.: Online testable reversible logic circuit design using NAND blocks. In International Symposium on Defect and Fault-Tolerance in VLSI Systems, pp. 324–331 (2004)
Vasudevan, D.P., Lala, P.K., Jia, D., Parkerson, J.P.: Reversible logic design with online testability. IEEE Trans. Instrum. Measur. 55, 406–414 (2006)
Kole, D.K., Rahaman, H., Das, D.K.: Synthesis of Online Testable Reversible Circuit. In International Symposium on Design and Diagnostic of Electronic Circuits and Systems, pp. 277–280 (2010)
Feynman, R.: Quantum mechanical computers. In Foundations of Physics, pp. 507–531 (1986)
Toffoli, T.: Reversible computing. In: de Bakker, J., van Leeuwen, J. (eds.) ICALP 1980. LNCS, vol. 85, pp. 632–644. Springer, Heidelberg (1980). https://doi.org/10.1007/3-540-10003-2_104
Fredkin, E., Toffoli, T.: Conservative logic. Int. J. Theor. Phys. 21, 219–253 (1982)
Mondal, B., Bhattacharjee, A., Bandyopadhyay, C., Rahaman, H.: An approach for detection of node displacement fault (NDF) in reversible circuit. In IEEE Symposium on VLSI Design and Test, pp. 605–616 (2019)
Wille, R., Grosse, D., Teuber, L., Dueck, G., W., Drechsler, R.: Revlib: An online resource for reversible functions and reversible circuits. In 38th ISMVL, pp. 220–225 (2008)
Farazmand, M., Zamani, M., Tahoori, M.B.: Online fault testing of reversible logic using dual rail coding. In Proceedings of International On-Line Testing Symposium, pp. 204–205 (2010)
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Mondal, B., Kar, U.N., Bandyopadhyay, C., Roy, D., Rahaman, H. (2022). An Online Testing Technique for the Detection of Control Nodes Displacement Faults (CNDF) in Reversible Circuits. In: Shah, A.P., Dasgupta, S., Darji, A., Tudu, J. (eds) VLSI Design and Test. VDAT 2022. Communications in Computer and Information Science, vol 1687. Springer, Cham. https://doi.org/10.1007/978-3-031-21514-8_22
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