Abstract
With the serial development of neural network models, choosing a superior platform for these complex computing applications is essential. Field-Programmable Gate Array (FPGA) is gradually becoming an accelerating platform that balances power and performance. The design of architecture in neural network accelerator based on FPGA is about two categories, stream and single-engine. Both design paradigms have advantages and disadvantages. The stream is easier to achieve high performance because of model customization but has low kernel compatibility. The single-engine is more flexible but has more scheduling overhead. Therefore, this work proposes a new design paradigm for the neural network accelerator based on FPGA, called the Multi-clusters (MC), which combines the characteristics of the above two design categories. We divide the original network model according to the calculated features. Then, different cores are designed to map these parts separately for efficient execution. The fine-grained pipeline is performed inside the cores. Multiple cores are executed by software scheduling and implement a coarse-grained schedule, thereby improving the overall computing performance. The experimental results show that the accelerator with the MC category achieved 39.7\(\times \) times improvement of performance and 7.9\(\times \) times improvement of energy efficiency compared with CPU and GPU, and finally obtained nearly 680.3 GOP/s computing performance in the peek.
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Acknowledgments
This work was supported in part by the National Key R &D Program of China under Grants 2017YFA0700900 and 2017YFA0700903, in part by the National Natural Science Foundation of China under Grants 62102383, 61976200, and 62172380, in part by Jiangsu Provincial Natural Science Foundation under Grant BK20210123, in part by Youth Innovation Promotion Association CAS under Grant Y2021121, and in part by the USTC Research Funds of the Double First-Class Initiative under Grant YD2150002005.
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Wang, T., Gong, L., Wang, C., Yang, Y., Gao, Y. (2022). Multi-clusters: An Efficient Design Paradigm of NN Accelerator Architecture Based on FPGA. In: Liu, S., Wei, X. (eds) Network and Parallel Computing. NPC 2022. Lecture Notes in Computer Science, vol 13615. Springer, Cham. https://doi.org/10.1007/978-3-031-21395-3_14
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DOI: https://doi.org/10.1007/978-3-031-21395-3_14
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