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A Formal Methodology for Verifying Side-Channel Vulnerabilities in Cache Architectures

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Formal Methods and Software Engineering (ICFEM 2022)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 13478))

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Abstract

Security-aware CPU caches have been designed to mitigate side-channel attacks and prevent information leakage. How to validate the effectiveness of these designs remains an unsolved problem. Prior works assess the security of architectures empirically without a formal guarantee, making the evaluation results less convincing. In this paper, we propose a comprehensive methodology based on formal methods for security verification of cache architectures. Specifically, we design an entropy-based noninterference reasoning framework with two unwinding conditions to assess the information leakage of the cache designs. The reasoning framework quantifies the dependency relationships by the mutual information between the distributions of input and output of side channels. Given a cache design, we formalize its behavior specification along with the cache layouts into an abstract state machine, to instantiate the parameterized reasoning framework that discloses any potential vulnerabilities. We use our methodology to assess eight state-of-the-art cache architectures to demonstrate reliability as well as flexibility.

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Notes

  1. 1.

    We follow the Isabelle/HOL definition where the cardinality of infinite sets is zero.

  2. 2.

    Interested readers can refer here for the reasoning framework and verification cases.

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Acknowledgements

This work has been supported in part by Singapore National Research Foundation under its National Cybersecurity R &D Programme (NCR Award NRF2018 NCR-NCR009-0001), Singapore Ministry of Education (MOE) AcRF Tier 1 RS02/19, NTU Start-up grant, and the National Natural Science Foundation of China (NSFC) under the Grant No. 62132014 and by Key R &D Program of Zhejiang Province under the Grant No. 62132014.

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Correspondence to Ke Jiang or Tianwei Zhang .

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Jiang, K., Zhang, T., Sanán, D., Zhao, Y., Liu, Y. (2022). A Formal Methodology for Verifying Side-Channel Vulnerabilities in Cache Architectures. In: Riesco, A., Zhang, M. (eds) Formal Methods and Software Engineering. ICFEM 2022. Lecture Notes in Computer Science, vol 13478. Springer, Cham. https://doi.org/10.1007/978-3-031-17244-1_12

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  • DOI: https://doi.org/10.1007/978-3-031-17244-1_12

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