Abstract
This chapter describes the verification process that students should be familiar with and provides two examples. The first example shows how a VHDL testbench can read input test vectors from a file and then write resulting vectors to a file. Matlab is used to create the test vectors and to check if the output is correct. The second example shows how to incorporate a Quartus IP component (ROM) in the verification process and how to account for latencies through the testbench.
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Snider, R. (2023). Chapter 8: Introduction to Verification. In: Advanced Digital System Design using SoC FPGAs. Springer, Cham. https://doi.org/10.1007/978-3-031-15416-4_8
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DOI: https://doi.org/10.1007/978-3-031-15416-4_8
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