Abstract
Numerous security threats are emerging from untrusted players in the integrated circuit (IC) ecosystem. Among them, reverse engineering practices with the intent to counterfeit, overproduce, or modify an IC are worrying. In recent years, various techniques have been proposed to mitigate the aforementioned threats but no technique seems to be adequate to hide the hierarchy of a design. Such ability to obfuscate the hierarchy is particularly important for designs that contain repeated modules. In this paper, we propose a novel way to obfuscate such designs by leveraging conventional logic synthesis. We exploit multiple optimizations that are available in the synthesis tool to create design diversity. Our security analysis, performed by using the DANA reverse engineering tool, confirms the significant impact of these optimizations on obfuscation. Among the many considered obfuscated design instances, users can find options that incur very small overheads while still confusing the work of a reverse engineer.
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Change history
27 October 2022
In an older version of this paper, there was a spelling error in the name of the corresponding author. It was incorrectly written as “Zail Ul Abideen”. This has been corrected to “Zain Ul Abideen”.
Notes
- 1.
For Cadence Genus, these attributes are lp_insert_clock_gating, auto_ungroup, dp_analytical_opt, br_seq_in_out_phase_opto, max_transition and retime -min_delay, retime -min_area.
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This work has been partially conducted in the project “ICT programme” which was supported by the European Union through the ESF.
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Basiashvili, G., Abideen, Z.U., Pagliarini, S. (2022). Obfuscating the Hierarchy of a Digital IP. In: Orailoglu, A., Reichenbach, M., Jung, M. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2022. Lecture Notes in Computer Science, vol 13511. Springer, Cham. https://doi.org/10.1007/978-3-031-15074-6_19
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