Abstract
The extent of this work is to plan and execute an ASIC (application-specific integrated circuit)-like reconfigurable architectural algorithm. A practical engineering SDR (software-defined radio) baseband (BB) receiver collector has just been inferred which is equipped for getting both OFDM (orthogonal frequency-division multiplexing) and stage-adjusted signs.
This work includes the estimation of computational complexities of different sub-blocks of the collector receiver. The outcomes acquired are utilized for the distinguishing proof of sub-hinders with comparative computational complexities in the receivers. The FIR (finite impulse response) and FFT (fast Fourier transform) functional unit blocks are recognized as the most computationally escalated parts and have been additionally broke down for computational necessities and equipment execution in the receivers. A coarse-grained, powerfully reconfigurable, tile-based equipment engineering is proposed to implement the calculations. There are nine independent tiles (information preparing components) in the framework. The self-sufficient nature of a tile permits simple adaptability and testability of the framework. The structure is finished utilizing 16-bit settled point information organized and is contrasted and the floating point programming execution.
The proposed execution is contrasted and the usage on the Montium tile processor (TP) (Kapoor, A Reconfigurable Architecture of Software-Defined-Radio for Wireless Local Area Networks, 2005), as far as area and speed parameters are concerned. This correlation demonstrates a region decrease of around multiple times in our design contrasted with the Montium TP-based execution. This decrease comes to the detriment of restricted adaptability. The FFT execution done is additionally contrasted as well as different other FFT usages. This examination demonstrates each performance/adaptability and exchange between these usage implementations.
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References
A. Kapoor, A Reconfigurable Architecture of Software-Defined-Radio for Wireless Local Area Networks, 2005
A. Kumar Kaushik, A Comparative Study of Software Defined Radio and Cognitive Radio Network Technology Security, pp. 104–110
M.B. Blanton, An FPGA software-defined ultra wideband transceiver. Master Sci. (2006)
X. Zhang, J. Ansari, M. Arya, P. Mähönen, Exploring parallelization for medium access schemes on many-core software defined radio architecture. Proc. Second Work. Softw. Radio Implement. Forum - SRIF 13, 37 (2013)
F. Buchali, F. Steiner, G. Böcherer, L. Schmalen, P. Schulte, W. Idler, Rate adaptation and reach increase by probabilistically shaped 64-QAM: An experimental demonstration. J. Lightwave Technol. 34(7), 1599–1609 (2016)
C. Zhang, Dynamically reconfigurable architectures for real-time baseband processing, no. May. 2014
L. Zhao, H. Shankar, A. Nachum, 40G QPSK and DQPSK modulation, Inphi Corporation, 2008
P. Dong, C. Xie, L. Chen, L.L. Buhl, Y.-K. Chen, 112-Gb/s monolithic PDM-QPSK modulator in silicon. Opt. Express 20(26), B624–B629 (2012)
H.D. Nataraj Urs, V.S. Reddy, Implementation and analysis of low frequency transceiver for SDR platforms. J. Adv. Res. Dyn. Control Syst. 10(04–Special Issue), 1–9 (2018)
C.Y. Chen, F.H. Tseng, K. Di Chang, H.C. Chao, J.L. Chen, Reconfigurable software defined radio and its applications. Tamkang J. Sci. Eng. 13(1), 29–38 (2010)
P. Suarez-Casal, A. Carro-Lagoa, J. A. Garćia-Naya, L. Castedo, A multicore SDR architecture for reconfigurable WiMAX downlink, in Proceedings of 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD) 2010, no. Cc, pp. 801–804, 2010
H. Goyal, J. Saxena, S. Dewra, Performance evaluation of OWC using different modulation techniques. J. Opt. Commun. 37(4), 33–35 (2016)
V. Kumar, H.D. Nataraj Urs, R.V.S. Reddy, Software defined radio: Advancement to cognitive radio and basic challenges in spectrum sensing. Asian J. Eng. Technol. Innov. 4(7), 166–169 (2016)
C. Chaitra, H.D. Nataraj Urs, Performance of SDR transceiver using different modulation techniques. Int. J. Adv. Eng. Res. Sci. 3(5) (2016). ISSN: 2349-6495
M.S. Karpe, A.M. Lalge, S.U. Bhandari, Reconfiguration challenges & design techniques in software defined radio. Int. J. Adv. Comput. Res. (2013)
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Nataraj Urs, H.D., Venkata Siva Reddy, R., Gudodagi, R., Sudharshan, K.M., Aravind, B.N. (2023). A Novel Algorithm for Reconfigurable Architecture for Software-Defined Radio Receiver on Baseband Processor for Demodulation. In: Awasthi, S., Sanyal, G., Travieso-Gonzalez, C.M., Kumar Srivastava, P., Singh, D.K., Kant, R. (eds) Sustainable Computing. Springer, Cham. https://doi.org/10.1007/978-3-031-13577-4_11
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