Abstract
Input buffers (IBs) for driving analog-to-digital converters (ADCs) in direct down-conversion radio frontends are normally operated with supply voltages higher than the nominal, mainly due to bandwidth (BW) and dynamic linearity constraints. Therefore, several voltage-regulators are required as well as the need of having I/O devices capable of handling such voltages. An energy-efficient input buffer architecture is presented in this paper and fairly compared to other existing IB realizations using a standard 1.2-V 130-nm CMOS technology as reference. The proposed new architecture presents better dynamic performance, and it can be readily used to drive moderate-resolution ADCs without requiring either a higher supply voltage or any non-standard I/O devices.
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References
Dermit, D., et al.: A 1.67-GSps TI 10-Bit Ping-Pong SAR ADC With 51-dB SNDR in 16-nm FinFET. IEEE Solid-State Circ. Lett. 3, 150–153 (2020)
Farag, F.A.: High performance CMOS buffer amplifier with offset cancellation. In: Saudi International Electronics, Communications and Photonics Conference, pp. 1–4 (2013)
Gray, P.R., Meyer, R.G., Hurst, P.J., Lewis, S.H.: Analysis and Design of Analog Integrated Circuits, 4th edn. Wiley, Hoboken (2001)
Kong, Y., Xu, S., Yang, H.: An ultra low output resistance and wide swingvoltage follower. In: International Conference on Communications, Circuits and Systems, pp. 1007–1010 (2007)
Rapakko, H., Kostamovaara, J.: On the performance and use of an improved source-follower buffer. IEEE Trans. Circ. Syst. I: Regul. Pap. 54(3), 504–517 (2007)
Vaz, B., et al.: A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC. In: IEEE International Solid-State Circuits Conference (ISSCC), pp. 276–277 (2017)
Fan, X., Chan, P.K.: Analysis and design of low-distortion CMOS source followers. Trans. Circ. Syst. I Regul. Pap. 52(8), 1489–1501 (2005)
Xing, G., Lewis, S.H., Viswanathan, T.R.: A unity-gain buffer with reduced offset and gain error. In: IEEE Custom Integrated Circuits Conference 2006, pp. 825–828 (2006)
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Leonardo, D., Goes, J. (2022). An Energy-Efficient Wideband Input-Buffer for High-Speed CMOS ADCs. In: Camarinha-Matos, L.M. (eds) Technological Innovation for Digitalization and Virtualization. DoCEIS 2022. IFIP Advances in Information and Communication Technology, vol 649. Springer, Cham. https://doi.org/10.1007/978-3-031-07520-9_18
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DOI: https://doi.org/10.1007/978-3-031-07520-9_18
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