Abstract
In this chapter, the design of the circuits presented in this book is analyzed, and a design tool based on the operation-point is introduced as an alternative to the transistor sizing of the ULV circuits. Additionally, an improvement on a semi-automated tool is proposed using the operation point design approach. The proposed tools can be employed to design and to optimize analog ULV circuits to reduce the design effort required by the traditional design methodologies.
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Notes
- 1.
M1x and M2x are referred only to give generic names for the transistors and are not physical devices.
References
P.E. Allen, D.R. Holberg, CMOS Analog Circuit Design, 2nd edn. (Oxford, New York, 2002)
K. Antreich, J. Eckmueller, H. Graeb, M. Pronath, F. Schenkel, R. Schwencker, S. Zizala, WiCkeD: analog circuit synthesis incorporating mismatch, in Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, Orlando (IEEE, New York, 2000), pp. 511–514. https://doi.org/10.1109/CICC.2000.852720
S. Balkir, G. Dundar, A.S. Ogrenci, Analog VLSI Design Automation, vol. 650 (CRC press, Boca Raton, 2003)
D.M. Binkley, Tradeoffs and Optimization in Analog Cmos Design, vol. 2 (Wiley, Chichester, 2007)
R.A.S. Braga, H.C. Ferreira, G.D. Colletta, O.O. Dutra, Calibration-less nauta OTA operating at 0.25-V power supply in a 130-nm digital CMOS process, in 2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS 2015) (2017), pp. 12–15
P.G. Drennan, C.C. McAndrew, Understanding MOSFET mismatch for analog design. IEEE J. Solid-State Circ. 38(3), 450–456 (2003)
F. El-Turky, E. Perry, BLADES: an artificial intelligence approach to analog circuit design. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 8(6), 680–692 (1989). https://doi.org/10.1109/43.31523
L.H.C. Ferreira, S. Member, S.R. Sonkusale, S. Member, A 60-dB gain OTA operating at 0.25-V power supply in 130-nm digital CMOS process. IEEE Trans. Circ. Syst. I: Regul. Pap. 61(6), 1609–1617 (2014)
C. Galup-Montoro, M.C. Schneider, I.J.B. Loss, Series-parallel association of FET’s for high gain and high frequency applications. IEEE J. Solid-State Circ. 29(9), 1094–1101 (1994). https://doi.org/10.1109/4.309905
P. Giacomelli, M. Schneider, C. Galup-Montoro, MOSVIEW: a graphical tool for MOS analog design, in Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE’03, Anaheim (IEEE Computer Society, New York, 2003), pp. 43–44 https://doi.org/10.1109/MSE.2003.1205247
H.E. Graeb, Analog Design Centering and Sizing (Springer, Dordrecht, 2007)
I. Guerra-Gómez, T. McConaghy, E. Tlelo-Cuautle, Operating-point driven formulation for analog computer-aided design. Analog Integr. Circ. Signal Process. 74(2), 345–353 (2013)
P.G.A. Jespers, B. Murmann, Systematic Design of Analog CMOS Circuits (Cambridge University Press, Cambridge, 2017)
B. Liu, M. Pak, X. Zheng, G. Gielen, A novel operating-point driven method for the sizing of analog IC. Proc. - IEEE Int. Symp. Circ. Syst. (1), 781–784 (2011). https://doi.org/10.1109/ISCAS.2011.5937682
N. Lourenço, R. Martins, A. Canelas, R. Póvoa, N. Horta, AIDA: layout-aware analog circuit-level sizing with in-loop layout generation. Integr. VLSI J. 55, 1–14 (2016)
H.C. Ou, K.H. Tseng, J.Y. Liu, I.P. Wu, Y.W. Chang, Layout-dependent effects-aware analytical analog placement. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 35(8), 1243–1254 (2016). https://doi.org/10.1109/TCAD.2015.2501293
R. Phelps, M. Krasnicki, R.A. Rutenbar, L.R. Carley, J.R. Hellums, Anaconda : simulation-based synthesis of analog circuits via stochastic pattern search. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 19(6), 703–717 (2000)
B. Razavi, Design of Analog CMOS Integrated Circuits, vol. 6 (McGraw-Hill, New York, 2001). https://doi.org/10.1111/j.1151-2916.1994.tb07040.x
M.C. Schneider, C. Galup-Montoro, CMOS Analog Design Using All-Region MOSFET Modeling, 1st edn. (Cambridge University Press, Cambridge, 2010)
L.C. Severo, W.A.M.V. Noije, An optimization-based design methodology with PVT analysis for ultra-low voltage analog ICs, in Conference on PhD Research in Microelectronics and Electronics (PRIME), Lisbon (IEEE, New York, 2016), pp. 1–4
L.C. Severo, A. Girardi, A.B. de Oliveira, F.N. Kepler, M.C. Cera, Simulated annealing to improve analog integrated circuit design: trade-offs and implementation issues, in Simulated Annealing - Single and Multiple Objective Problems (Intech, London, 2012), pp. 261–283
L.C. Severo, F.N. Kepler, A.G. Girardi, Automatic synthesis of analog integrated circuits including efficient yield optimization, in Computational Intelligence in Analog and Mixed-Signal (AMS) and Radio-Frequency (RF) Circuit Design (Springer International Publishing, Cham, 2015), pp. 29–58
D. Stefanovic, M. Kayal, Structured Analog CMOS Design, vol. 53, 1st edn. (Springer Netherlands, Dordrecht, 2009)
Y. Tsividis, Operation and Modeling of the MOS Transistor, 2nd edn. (Oxford University Press, New York, 2003). ISBN:978-0-1951-7015-3
T.O. Weber, Síntese de CIs analógicos em nível de circuito e sistema utilizando métodos modernos de otimização. PhD thesis, Unversidade de São Paulo, 2015
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Severo, L.C., Van Noije, W.M.A. (2022). Design Methodology for ULV Circuits. In: Ultra-low Voltage Low Power Active-RC Filters and Amplifiers for Low Energy RF Receivers . Springer, Cham. https://doi.org/10.1007/978-3-030-90103-5_4
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