Abstract
In order to achieve remote interconnection between ethernet and 30-channel pulse code modulation (E1) heterogeneous networks, an ethernet mapping high-level data link control (HDLC) circuit is designed. The design adopts a “top-down” design approach by encapsulating ethernet frames into HDLC frames, dividing the design into two modules: transmit and receive, and then into encapsulation and decapsulation modules according to specific functions. Different from the traditional design, this paper proposes a new design idea and adds four modules: cyclic redundancy check 32 (CRC32) generation, CRC32 checking, insertion error and error monitoring. Verilog description language is used for circuit design, and modelsim is used for functional simulation. The simulation verifies that the ethernet data is recovered from the original ethernet data after a series of processing by HDLC encapsulation and decapsulation modules.
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References
Graber, H., Roche, H.: Multi-service switches and the service intelligent optical architecture for SONET/SDH metro networks. Bell Labs Tech. J. 8(2), 111–127 (2010)
Eramo, V., Listanti, M., Lavacca, F.G.: Dimensioning models of optical WDM rings in Xhaul access architectures for the transport of ethernet/CPRI traffic. Appl. Sci. 8(4), 612–613 (2018)
Ikegawa, T.: Queuing network modeling for performance analysis of HDLC based protocols. Electron. Commun. Jpn. (Part I Commun.) 76(10), 49–58 (2010)
Valcarenghi, L., Kondepu, K., Castoldi, P.: Time-versus size-based CPRI in ethernet encapsulation for next generation reconfigurable fronthaul. IEEE/OSA J. Opt. Commun. Netw. 9(9), 64–73 (2017)
Wenhui, L., Chi, Z., Hong, Y., Wensheng, W.: Study and implementation of E1/Ethernet interconnect scheme based on FPGA. Commun. Technol. 43(12), 187–189 (2010)
Jinsong, Z., Zhengyu, L., Xiaofu, W.: Communication channel based on HDLC protocol. Commun. Technol. 49(03), 368–373 (2016)
Cheng, D., Haisheng, H., Xin, L., Zhiguo, Z.: HDLC frame processing circuit based on E1. Opt. Commun. Technol. 45(02), 28–31 (2021)
Mliki, H., Chaari, L., Kamoun, L.: A comprehensive survey on carrier ethernet congestion management mechanism. J. Netw. Comput. Appl. 47, 107–130 (2015)
Yu, L., Bin, Z., Dongming, X.: FPGA design and implementation of HDLC protocol in China mobile standard protocol converter. Electron. Prod. world 18(06), 58–60 (2011)
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Lv, M., Huang, H., Li, X. (2022). An Ethernet Mapping High-Level Data Link Control Circuit Design. In: Xie, Q., Zhao, L., Li, K., Yadav, A., Wang, L. (eds) Advances in Natural Computation, Fuzzy Systems and Knowledge Discovery. ICNC-FSKD 2021. Lecture Notes on Data Engineering and Communications Technologies, vol 89. Springer, Cham. https://doi.org/10.1007/978-3-030-89698-0_122
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DOI: https://doi.org/10.1007/978-3-030-89698-0_122
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