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On the Hardness of the Determinant: Sum of Regular Set-Multilinear Circuits

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Fundamentals of Computation Theory (FCT 2021)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 12867))

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Abstract

In this paper, we study the computational complexity of the commutative determinant polynomial computed by a class of set-multilinear circuits which we call regular set-multilinear circuits. Regular set-multilinear circuits are commutative circuits with a restriction on the order in which they can compute polynomials. A regular circuit can be seen as the commutative analogue of the ordered circuit defined by Hrubes, Wigderson and Yehudayoff [5]. We show that if the commutative determinant polynomial has small representation in the sum of constantly many regular set-multilinear circuits, then the commutative permanent polynomial also has a small arithmetic circuit.

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Correspondence to S. Raja .

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Raja, S., Bharadwaj, G.V.S. (2021). On the Hardness of the Determinant: Sum of Regular Set-Multilinear Circuits. In: Bampis, E., Pagourtzis, A. (eds) Fundamentals of Computation Theory. FCT 2021. Lecture Notes in Computer Science(), vol 12867. Springer, Cham. https://doi.org/10.1007/978-3-030-86593-1_30

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  • DOI: https://doi.org/10.1007/978-3-030-86593-1_30

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-86592-4

  • Online ISBN: 978-3-030-86593-1

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