Abstract
In the paper we review high-level synthesis software tools for special-purpose hardware circuit configurations for reconfigurable computer systems that consist of a numerous FPGA chips interconnected by a spatial communication system. The distinctive feature of the software tools is mapping of the source C-program into the completely parallel form (an information graph) which is transformed into the resource-independent parallel pipeline form and automatically scaled. As a result, a reasonable solution for an available hardware resource is generated. The information graph consists of tasks with data dependencies and different rates of data flows. The parallel-pipeline form is scaled by the methods of performance reduction with the same reduction coefficient for all subgraphs. Owing to this, the different fragments of the problem have the same data processing rate. The result of the transformations is balanced and reasonable computing structure of the whole problem with the same rate of data flows among its fragments. Besides, we review the results of the suggested methods applied to several implemented problems.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
Voevodin, V.V., Voevodin, Vl.V.: Parallel Computing. BHV-Petersburg (2002)
Mittal, S., Vetter, J.S.: A survey of CPU-GPU heterogeneous computing techniques. ACM Comput. Surv. 47(4), 1–35 (2015)
Trimberger, S.M.: Three ages of FPGAs: a retrospective on the first thirty years of FPGA technology. Proc. IEEE 103(3), 318–331 (2015)
Multiprocessor computer systems with reconfigurable architecture. http://superevm.ru/index.php?page=hardware-2. Accessed 27 May 2021
Levin, I., et al.: Software development tools for FPGA-based reconfigurable systems programming. In: Voevodin, V., Sobolev, S. (eds.) RuSCDays 2019. CCIS, vol. 1129, pp. 625–640. Springer, Cham (2019). https://doi.org/10.1007/978-3-030-36592-9_51
Dordopulo, A.I., Levin, I.I.: Performance reduction for automatic development of parallel applications for reconfigurable computer systems. Supercomput. Front. Innov. 7(2), 4–23 (2020)
Nane, R., et al.: A survey and evaluation of FPGA high-level synthesis tools. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(10), 1591–1604 (2016)
Nane, R., Sima, V.-M., Olivier, B., Meeuws, R., Yankova, Y., Bertels, K.: DWARV 2.0: a cosy-based C-to-VHDL hardware compiler. In: FPL, pp. 619–622 (2012)
Pilato, C., Ferrandi, F.: Bambu: a modular framework for the high level synthesis of memory-intensive applications. In: FPL, pp. 1–4 (2013)
Canis, A., et al.: LegUp: high-level synthesis for FPGA-based processor/accelerator systems. In: ACM FPGA, pp. 33–36 (2011)
Intel HLS Compiler. https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/hls-compiler.html?wapkw=Intel%20HLS%20compiler. Accessed 27 May 2021
Cadence Stratus HLS. https://www.cadence.com/en_US/home/tools/digital-design-and-signoff/synthesis/stratus-high-level-synthesis.html. Accessed 27 May 2021
Make Slow Software Run Fast with Vivado HLS. https://www.xilinx.com/publications/xcellonline/run-fast-with-Vivado-HLS.pdf. Accessed 27 May 2021
Vitis Unified Software Platform Documentation. Application Acceleration Development. https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug1393-vitis-application-acceleration.pdf. Accessed 27 May 2021
Kalyaev, I.A., Levin, I.I., Semernikov, E.A., Shmoilov, V.I.: Reconfigurable Multipipeline Computing Structures. Nova Science Publishers, New York (2012)
Bielecki, W., Palkowski, M.: Perfectly nested loop tiling transformations based on the transitive closure of the program dependence graph. In: Wiliński, A., El Fray, I., Pejaś, J. (eds.) Soft Computing in Computer and Information Science. AISC, vol. 342, pp. 309–320. Springer, Cham (2015). https://doi.org/10.1007/978-3-319-15147-2_26
Devan, P.S., Kamat, R.K.: A review – LOOP dependence analysis for parallelizing compiler. Int. J. Comput. Sci. Inf. Technol. 5(3) (2014). https://www.ijcsit.com/docs/Volume%205/vol5issue03/ijcsit20140503305.pdf. Accessed 27 May 2021
Giorgi, R., Khalili, F., Procaccini, M.: Translating timing into an architecture: the synergy of COTSon and HLS (domain expertise—designing a computer architecture via HLS). Int. J. Reconfig. Comput 2019 (2019). https://downloads.hindawi.com/journals/ijrc/2019/2624938.pdf. Accessed 27 May 2021. https://doi.org/10.1155/2019/2624938
Licht, J., Besta, M., Meierhans, S., Hoefler, T.: Transformations of high-level synthesis codes for high-performance computing, 23 November 2020. https://doi.org/10.1109/TPDS.2020.3039409
Levin, I., Dordopulo, A., Fedorov, A., Kalyaev, I.: Reconfigurable computer systems: from the first FPGAs towards liquid cooling systems. Supercomput. Front. Innov. 3(1), 22–40 (2016)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2021 Springer Nature Switzerland AG
About this paper
Cite this paper
Dordopulo, A.I., Levin, I.I., Gudkov, V.A., Gulenok, A.A. (2021). High-Level Synthesis of Scalable Solutions from C-Programs for Reconfigurable Computer Systems. In: Malyshkin, V. (eds) Parallel Computing Technologies. PaCT 2021. Lecture Notes in Computer Science(), vol 12942. Springer, Cham. https://doi.org/10.1007/978-3-030-86359-3_7
Download citation
DOI: https://doi.org/10.1007/978-3-030-86359-3_7
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-86358-6
Online ISBN: 978-3-030-86359-3
eBook Packages: Computer ScienceComputer Science (R0)