Abstract
Priority queues are fundamental abstract data types, often used to manage limited resources in parallel systems. Typical proposed parallel priority queue implementations are based on heaps or skip lists. In recent literature, skip lists have been shown to be the most efficient design choice for implementing priority queues. Though numerous intricate implementations of skip list based queues have been proposed in the literature, their performance is constrained by the high number of global atomic updates per operation and the high memory consumption, which are proportional to the number of sub-lists in the queue.
In this paper, we propose an alternative approach for designing lock-free linearizable priority queues, that significantly improves memory efficiency and throughput performance, by reducing the number of global atomic updates and memory consumption as compared to skip-list based queues. To achieve this, our new design combines two structures; a search tree and a linked list, forming what we call a Tree Search List Queue (TSLQueue). The leaves of the tree are linked together to form a linked list of leaves with a head as an access point. Analytically, a skip-list based queue insert or delete operation has at worst case \(O(\log {}n)\) global atomic updates, where n is the size of the queue. While the TSLQueue insert or delete operations require only 2 or 3 global atomic updates respectively. When it comes to memory consumption, TSLQueue exhibits O(n) memory consumption, compared to \(O(n\log {}n)\) worst case for a skip-list based queue, making the TSLQueue more memory efficient than a skip-list based queue of the same size. We experimentally show, that TSLQueue significantly outperforms the best previous proposed skip-list based queues, with respect to throughput performance.
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Notes
- 1.
Quiescent consistency semantics allow weaker object behaviour than strong consistency models like linearizability to allow for better performance.
- 2.
The ABA problem occurs when multiple processors access a shared location without noticing each others’ changes.
- 3.
CAS atomically compares the contents of a memory location with a given value and, only if they are the same, modifies the contents of that memory location.
- 4.
Fetch and xor atomically replaces the current value of a memory location with the result of bit-wise XOR of the memory location value, and returns the previous memory location value before the XOR.
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Acknowledgements and Data Availability Statement
The data sets and code generated and/or analysed during the current study are available in the Figshare repository: https://doi.org/10.6084/m9.figshare.14748420 [17]. This work has been supported by SIDA/Bright Project (317) under the Makerere-Sweden bilateral research programme 2015–2020, Mbarara University of Science and Technology and Swedish Research Council (Vetenskapsrådet) Under Contract No.: 2016-05360.
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Rukundo, A., Tsigas, P. (2021). TSLQueue: An Efficient Lock-Free Design for Priority Queues. In: Sousa, L., Roma, N., Tomás, P. (eds) Euro-Par 2021: Parallel Processing. Euro-Par 2021. Lecture Notes in Computer Science(), vol 12820. Springer, Cham. https://doi.org/10.1007/978-3-030-85665-6_24
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