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Pushing the Limits of Valiant’s Universal Circuits: Simpler, Tighter and More Compact

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Advances in Cryptology – CRYPTO 2021 (CRYPTO 2021)

Part of the book series: Lecture Notes in Computer Science ((LNSC,volume 12826))

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Abstract

A universal circuit (UC) is a general-purpose circuit that can simulate arbitrary circuits (up to a certain size n). Valiant provides a k-way recursive construction of UCs (STOC 1976), where k tunes the complexity of the recursion. More concretely, Valiant gives theoretical constructions of 2-way and 4-way UCs of asymptotic (multiplicative) sizes \(5n\log n\) and \(4.75 n\log n\) respectively, which matches the asymptotic lower bound \(\varOmega (n\log n)\) up to some constant factor.

Motivated by various privacy-preserving cryptographic applications, Kiss et al. (Eurocrypt 2016) validated the practicality of 2-way universal circuits by giving example implementations for private function evaluation. Günther et al. (Asiacrypt 2017) and Alhassan et al. (J. Cryptology 2020) implemented the 2-way/4-way hybrid UCs with various optimizations in place towards making universal circuits more practical. Zhao et al. (Asiacrypt 2019) optimized Valiant’s 4-way UC to asymptotic size \(4.5 n\log n\) and proved a lower bound \(3.64 n\log n\) for UCs under Valiant’s framework. As the scale of computation goes beyond 10-million-gate (\(n=10^7\)) or even billion-gate level (\(n=10^9\)), the constant factor in UC’s size plays an increasingly important role in application performance. In this work, we investigate Valiant’s universal circuits and present an improved framework for constructing universal circuits with the following advantages.

  • Simplicity. Parameterization is no longer needed. In contrast to those previous implementations that resorted to a hybrid construction combining \(k=2\) and \(k=4\) for a tradeoff between fine granularity and asymptotic size-efficiency, our construction gets the best of both worlds when configured at the lowest complexity (i.e., \(k=2\)).

  • Compactness. Our universal circuits have asymptotic size \(3n\log n\), improving upon the best previously known \(4.5n\log n\) by 33% and beating the \(3.64n\log n\) lower bound for UCs constructed under Valiant’s framework (Zhao et al., Asiacrypt 2019).

  • Tightness. We show that under our new framework the UC’s size is lower bounded by \(2.95 n\log n\), which almost matches the \(3n\log n\) circuit size of our 2-way construction.

We implement the 2-way universal circuit and evaluate its performance with other implementations, which confirms our theoretical analysis.

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Notes

  1. 1.

    Let us mention that there are other alternatives to PFE without using universal circuits, of which the most efficient one to date is the work by Katz and Malka [36].

  2. 2.

    It is typically assumed that a circuit C consists of AND gates and XOR gates. The size of C refers to the number of gates in C, and its multiplicative size is the number of AND gates. As a major performance indicator for Valiant’s (and our optimized) framework, the multiplicative size of a UC is roughly a quarter of its total size.

  3. 3.

    The edge embedding algorithm for constructing 2-way UC is simply a bipartite matching algorithm, while in contrast, a generic algorithm for k-way UC is much more complex and less efficient. Moreover, Valiant’s construction only explicitly handles the case \(n=B k^j\) for arbitrary \(j\in \mathbb {N^+}\) (i.e., the number of recursions) and small \(B\in \mathbb {N^+}\) (i.e., \(\mathsf {EUG}(B)\) is the initial EUG built from scratch). Optimization techniques [3, 30] are helpful in adapting to arbitrary n, especially for \(k=2\).

  4. 4.

    Note that the poles of \(\mathsf {EUG}_1(\lceil \frac{n}{k}\rceil -1)\) do not constitute the poles of the \(\mathsf {EUG}_1(n)\), but become X-switching nodes after merging with input/output nodes.

  5. 5.

    Recall that subscript 1 in \(\mathsf {EUG}_1(n)\) refers to its capability of edge embedding arbitrary \(\mathsf {DAG}_1(n)\), instead of that \(\mathsf {EUG}_1(n)\) is of fan-in/fan-out 1. In fact, an \(\mathsf {EUG}_1\) needs fan-in/fan-out 2 to cater for control nodes such as X/Y switching nodes.

  6. 6.

    No edge \((p_u,p_v)\in E_i\) (i.e., \(i=j\)) is considered, and the case for \(i>j\) is not possible as nodes are topologically sorted in the first place. Further, if there are multiple edges from a node in \(V_i\) to one in \(V_j\), then equally many copies of \((O_i,I_j)\) are added.

  7. 7.

    After merging, edge (\(out_i^t\),\(in_{i+1}^t\)) becomes a self-loop which is not included in \(E'_{vert}\).

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Acknowledgments

We are grateful to the authors of [3] for pointing out the issue in a previous version that our intermediate construction yields only a weak EUG, and for many helpful suggestions. Yu Yu, the corresponding author, was supported by the National Key Research and Development Program of China (Grant Nos. 2020YFA0309705 and 2018YFA0704701) and the National Natural Science Foundation of China (Grant Nos. 61872236 and 61971192). Jiang Zhang is supported by the National Natural Science Foundation of China (Grant Nos. 62022018, 61932019), the National Key Research and Development Program of China (Grant No. 2018YFB0804105). This work is also supported by Shandong Provincial Key Research and Development Program (Major Scientific and Technological Innovation Project, Grant No. 2019JZZY010133), Shandong Key Research and Development Program (Grant No. 2020ZLYS09).

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Authors and Affiliations

  1. Department of Computer Science and Engineering, Shanghai Jiao Tong University, 800 Dongchuan Road, Shanghai, 200240, China

    Hanlin Liu, Yu Yu, Shuoyao Zhao, Wenling Liu & Zhenkai Hu

  2. Shanghai Qi Zhi Institute, 701 Yunjin Road, Shanghai, 200232, China

    Yu Yu

  3. Shanghai Key Laboratory of Privacy-Preserving Computation, 701 Yunjin Road, Shanghai, 200232, China

    Yu Yu

  4. State Key Laboratory of Cryptology, P.O. Box 5159, Beijing, 100878, China

    Jiang Zhang

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  1. Columbia University, New York City, NY, USA

    Tal Malkin

  2. University of Michigan, Ann Arbor, MI, USA

    Chris Peikert

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Liu, H., Yu, Y., Zhao, S., Zhang, J., Liu, W., Hu, Z. (2021). Pushing the Limits of Valiant’s Universal Circuits: Simpler, Tighter and More Compact. In: Malkin, T., Peikert, C. (eds) Advances in Cryptology – CRYPTO 2021. CRYPTO 2021. Lecture Notes in Computer Science(), vol 12826. Springer, Cham. https://doi.org/10.1007/978-3-030-84245-1_13

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