Skip to main content
SpringerLink
Log in

SANSCrypt: Sporadic-Authentication-Based Sequential Logic Encryption

  • Conference paper
  • First Online:
VLSI-SoC: Design Trends (VLSI-SoC 2020)

Part of the book series: IFIP Advances in Information and Communication Technology ((IFIPAICT,volume 621))

Abstract

Sequential logic encryption is a countermeasure against reverse engineering of sequential circuits based on modifying the original finite state machine of the circuit such that the circuit enters a wrong state upon being reset. A user must apply a certain sequence of input patterns, i.e., a key sequence, for the circuit to transition to the correct state. The circuit then remains functional unless it is powered off or reset again. Most sequential encryption methods require the correct key to be applied only once. In this paper, we propose a novel Sporadic-Authentication-Based Sequential Logic Encryption method (SANSCrypt) that circumvents the potential vulnerability associated with a single-authentication mechanism. SANSCrypt adopts a new temporal dimension to logic encryption, by requiring the user to sporadically perform multiple authentications according to a protocol based on pseudo-random number generation. We provide implementation details of SANSCrypt and present a design that is amenable to time-sensitive applications. In SANSCrypt, the authentication task does not significantly disrupt the normal circuit operation, as it can be interrupted or postponed upon request from a high-priority task with minimal impact on the overall performance. Analysis and validation results on a set of benchmark circuits show that SANSCrypt offers a substantial output corruptibility if the key sequences are applied incorrectly. Moreover, it exhibits exponential resilience to existing attacks, including SAT-based attacks, while maintaining a reasonably low overhead.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 109.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 139.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 139.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Karri, R., Rajendran, J., Rosenfeld, K., Tehranipoor, M.: Trustworthy hardware: identifying and classifying hardware trojans. Computer 43(10), 39–46 (2010)

    Article  Google Scholar 

  2. Tehranipoor, M., Koushanfar, F.: A survey of hardware trojan taxonomy and detection. IEEE Des. Test Comput. 27(1), 10–25 (2010)

    Article  Google Scholar 

  3. Rajendran, J., et al.: Fault analysis-based logic encryption. IEEE Trans. Comput. 64(2), 410–424 (2013)

    Article  MathSciNet  Google Scholar 

  4. M. Yasin, Sengupta, A., Nabeel, M.T., Ashraf, M., Rajendran, J.J., Sinanoglu, O.: Provably-secure logic locking: from theory to practice. In: Proceedings of SIGSAC Conference Computer and Communications Security, pp. 1601–1618 (2017)

    Google Scholar 

  5. Yasin, M., Mazumdar, B., Rajendran, J.J., Sinanoglu, O.: SARLock: SAT attack resistant logic locking. In: IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 236–241 (2016)

    Google Scholar 

  6. Chakraborty, R.S., Bhunia, S.: HARPOON: an obfuscation-based SoC design methodology for hardware protection. IEEE Trans. Comput. Aid. Des. Integr. Circ. Syst. 28(10), 1493–1502 (2009)

    Google Scholar 

  7. Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran J.: CamoPerturb: secure IC camouflaging for minterm protection. In: 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 1–8 (2016)

    Google Scholar 

  8. Xiao, K., Forte, D., Tehranipoor, M.: Efficient and secure split manufacturing via obfuscated built-in self-authentication. In: IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 14–19 (2015)

    Google Scholar 

  9. Charbon, E.: Hierarchical watermarking in IC design. In: IEEE Proceedings of Custom Integrated Circuits Conference, pp. 295–298 (1998)

    Google Scholar 

  10. Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143 (2015)

    Google Scholar 

  11. Chakraborty, P., Cruz, J., Bhunia, S.: SURF: joint structural functional attack on logic locking. In: IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 181–190 (2019)

    Google Scholar 

  12. Shen, Y., Li, Y., Kong, S., Rezaei, A., Zhou, H.: SigAttack: new high-level sat-based attack on logic encryptions. In: Design, Automation and Test in Europe Conference and Exhibition (DATE), pp. 940–943 (2019)

    Google Scholar 

  13. Menon, V.V., et al.: System-level framework for logic obfuscation with quantified metrics for evaluation. In: Secure Development Conference (SecDev), pp. 89–100 (2019)

    Google Scholar 

  14. Hu, Y., Menon, V.V., Schmidt, A., Monson, J., French, M., Nuzzo, P.: Security-driven metrics and models for efficient evaluation of logic encryption schemes. In: ACM-IEEE International Confernce on Formal Methods and Models for System Design (MEMOCODE), pp. 1–5 (2019)

    Google Scholar 

  15. Sengar, G., Mukhopadhyay, D., Chowdhury, D.R.: Secured flipped scan-chain model for crypto-architecture. IEEE Trans. Comput. Aid. Des. Integr. Circ. Syst. 26(11), 2080–2084 (2007)

    Google Scholar 

  16. Paul, S., Chakraborty, R.S., Bhunia, S.: VIm-scan: a low overhead scan design approach for protection of secret key in scan-based secure chips. In: IEEE VLSI Test Symposium (VTS), pp. 455–460 (2007)

    Google Scholar 

  17. Wang, X., Zhang, D., He, M., Su, D., Tehranipoor, M.: Secure scan and test using obfuscation throughout supply chain. IEEE Trans. Comput. Aid. Des. Integr. Circ. Syst. 37(9), 1867–1880 (2017)

    Google Scholar 

  18. El Massad, M., Garg, S., Tripunitara, M.: Reverse engineering camouflaged sequential circuits without scan access. In: 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 33–40. IEEE (2017)

    Google Scholar 

  19. Shamsi, K., Li, M., Pan, D.Z., Jin, Y.: KC2: key-condition crunching for fast sequential circuit deobfuscation. In: Design, Automation and Test in Europe Conference and Exhibition (DATE), pp. 534–539 (2019)

    Google Scholar 

  20. Chakraborty, P., Cruz, J., Bhunia, S.: SAIL: machine learning guided structural analysis attack on hardware obfuscation. In: IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST), pp. 56–61 (2018)

    Google Scholar 

  21. Sisejkovic, D., Merchant, F., Reimann, L.M., Srivastava, H., Hallawa, A., Leupers, R.: Challenging the security of logic locking schemes in the era of deep learning: a neuroevolutionary approach. arXiv preprint arXiv:2011.10389 (2020)

  22. Hu, Y., Yang, K., Dutta Chowdhury, S., Nuzzo, P.: Risk-aware cost-effective design methodology for integrated circuit locking. In: Design, Automation and Test in Europe Conference and Exhibition (DATE), pp. 1182–1185. IEEE (2021)

    Google Scholar 

  23. Desai, A.R., Hsiao, M.S., Wang, C., Nazhandali, L., Hall, S.: Interlocking obfuscation for anti-tamper hardware. In: Proceedings of Cyber Security and Information Intelligence Research Workshop, pp. 1–4 (2013)

    Google Scholar 

  24. Kasarabada, Y., Raman, S.R.T., Vemuri, R.: Deep state encryption for sequential logic circuits. In: IEEE Computer Society Annual Symposium VLSI (ISVLSI), pp. 338–343 (2019)

    Google Scholar 

  25. Meade, T., Zhao, Z., Zhang, S., Pan, D., Jin, Y.: Revisit sequential logic obfuscation: attacks and defenses. In: IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–4 (2017)

    Google Scholar 

  26. Duvalsaint, D., Liu, Z., Ravikumar, A., Blanton, R.: Characterization of locked sequential circuits via ATPG. In: IEEE International Test Conference in Asia (ITC-Asia), pp. 97–102 (2019)

    Google Scholar 

  27. Bhargav-Spantzel, A., Squicciarini, A.C., Modi, S., Young, M., Bertino, E., Elliott, S.J.: Privacy preserving multi-factor authentication with biometrics. J. Comput. Secur. 15(5), 529–560 (2007)

    Article  Google Scholar 

  28. Brglez, F., Bryan, D., Kozminski, K.: Combinational profiles of sequential benchmark circuits. In: IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1929–1934 (1989)

    Google Scholar 

  29. Hu, Y., Yang, K., Nazarian, S., Nuzzo, P.: SANSCrypt: a sporadic-authentication-based sequential logic encryption scheme. In: IFIP/IEEE International Confefrence on Very Large Scale Integration (VLSI-SoC), pp. 129–134 (2020)

    Google Scholar 

  30. Meade, T., Jin, Y., Tehranipoor, M., Zhang, S.: Gate-level netlist reverse engineering for hardware security: control logic register identification. In: IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1334–1337 (2016)

    Google Scholar 

  31. Brunner, M., Baehr, J., Sigl, G.: Improving on state register identification in sequential hardware reverse engineering. In: IEEE International Symposium on Hardware Oriented Security and Trust (HOST) (2019)

    Google Scholar 

  32. Geist, J., et al.: RELIC-FUN: logic identification through functional signal comparisons. In: Proceedings of Design Automation Conference (DAC) (2020)

    Google Scholar 

  33. Dofe, J., Yu, Q.: Novel dynamic state-deflection method for gate-level design obfuscation. IEEE Trans. Comput. Aid. Des. Integr. Circ. Syst. 37, 273–285 (2018)

    Google Scholar 

  34. Biere, A., Cimatti, A., Clarke, E.M., Strichman, O., Zhu, Y.: Bounded model checking (2003)

    Google Scholar 

  35. Kasarabada, Y., Chen, S., Vemuri, R.: On SAT-based attacks on encrypted sequential logic circuits. In: International Symposium on Quality Electronic Design (ISQED), pp. 204–211 (2019)

    Google Scholar 

  36. Flajolet, P., Gardy, D., Thimonier, L.: Birthday paradox, coupon collectors, caching algorithms and self-organizing search. Discret. Appl. Math. 39(3), 207–229 (1992)

    Article  MathSciNet  Google Scholar 

  37. Silvaco: 45nm open cell library (2019)

    Google Scholar 

  38. Rahman, M.S., et al.: Dynamically obfuscated scan chain to resist oracle-guided attacks on logic locked design. IACR Cryptol. ePrint Arch., vol. 2019, p. 946 (2019)

    Google Scholar 

Download references

Acknowledgments

This work was supported in part by the Air Force Research Laboratory (AFRL) and the Defense Advanced Research Projects Agency (DARPA) under agreement number FA8650-18-1-7817.

Author information

Authors and Affiliations

  1. University of Southern California, Los Angeles, CA, 90089, USA

    Yinghua Hu, Kaixin Yang, Shahin Nazarian & Pierluigi Nuzzo

Authors
  1. Yinghua Hu
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Kaixin Yang
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Shahin Nazarian
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Pierluigi Nuzzo
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Yinghua Hu .

Editor information

Editors and Affiliations

  1. Politecnico di Torino, Turin, Italy

    Andrea Calimera

  2. University of Utah, Salt Lake City, UT, USA

    Pierre-Emmanuel Gaillardon

  3. Technion – Israel Institute of Technology, Haifa, Israel

    Kunal Korgaonkar

  4. Technion – Israel Institute of Technology, Haifa, Israel

    Shahar Kvatinsky

  5. Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil

    Ricardo Reis

Rights and permissions

Reprints and permissions

Copyright information

© 2021 IFIP International Federation for Information Processing

About this paper

Check for updates. Verify currency and authenticity via CrossMark

Cite this paper

Hu, Y., Yang, K., Nazarian, S., Nuzzo, P. (2021). SANSCrypt: Sporadic-Authentication-Based Sequential Logic Encryption. In: Calimera, A., Gaillardon, PE., Korgaonkar, K., Kvatinsky, S., Reis, R. (eds) VLSI-SoC: Design Trends. VLSI-SoC 2020. IFIP Advances in Information and Communication Technology, vol 621. Springer, Cham. https://doi.org/10.1007/978-3-030-81641-4_12

Download citation

  • DOI: https://doi.org/10.1007/978-3-030-81641-4_12

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-81640-7

  • Online ISBN: 978-3-030-81641-4

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics

Societies and partnerships

Search

Navigation