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Register Allocation

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SSA-based Compiler Design

Abstract

Register allocation maps the variables of a program to physical memory locations: usually either CPU registers or the main memory. As there is only a small number of registers available in a CPU, the task of register allocation is also to decide which variables should be evicted from registers and at which program points to store and load them from memory (spilling). Furthermore, register allocation has to remove spurious copy instructions (copy coalescing) inserted by previous phases in the compilation process and to deal with allocation restrictions that the instruction set architecture and the runtime system impose (register targeting). Classical register allocation algorithms address these different issues with either complex and sometimes expensive schemes (usually graph-based), or simpler and faster (but less efficient) algorithms such as linear scan. The goal of this chapter is to illustrate how SSA form can help in designing both simpler and faster schemes with similar or even better quality than the most complex existing ones.

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Notes

  1. 1.

    This definition of interference by liveness is an over-approximation (see Sect. 2.6 of Chap. 2), and there are refined definitions that create less interferences (see Chap. 21). However, in this chapter, we will restrict ourselves to this definition and assume that two variables whose live ranges intersect cannot be assigned the same register.

  2. 2.

    Hence, the terms “register” and “colour” will be used interchangeably in this chapter.

  3. 3.

    See Fig. 13.1 of Chap. 13 for a visualization of program points.

  4. 4.

    In a chordal graph, also called a triangulated graph, every cycle of length 4 or more has (at least) one chord (i.e., an edge joining two non-consecutive edges in the cycle).

  5. 5.

    Observe that, with a program originally under SSA form, practical implementation may still choose to interleave the process of spilling and coalescing/colouring. Result will be unchanged, but speed might be impacted.

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Correspondence to Fabrice Rastello .

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Tichadou, F.B., Rastello, F. (2022). Register Allocation. In: Rastello, F., Bouchez Tichadou, F. (eds) SSA-based Compiler Design. Springer, Cham. https://doi.org/10.1007/978-3-030-80515-9_22

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  • DOI: https://doi.org/10.1007/978-3-030-80515-9_22

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