Abstract
Register allocation maps the variables of a program to physical memory locations: usually either CPU registers or the main memory. As there is only a small number of registers available in a CPU, the task of register allocation is also to decide which variables should be evicted from registers and at which program points to store and load them from memory (spilling). Furthermore, register allocation has to remove spurious copy instructions (copy coalescing) inserted by previous phases in the compilation process and to deal with allocation restrictions that the instruction set architecture and the runtime system impose (register targeting). Classical register allocation algorithms address these different issues with either complex and sometimes expensive schemes (usually graph-based), or simpler and faster (but less efficient) algorithms such as linear scan. The goal of this chapter is to illustrate how SSA form can help in designing both simpler and faster schemes with similar or even better quality than the most complex existing ones.
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Notes
- 1.
This definition of interference by liveness is an over-approximation (see Sect. 2.6 of Chap. 2), and there are refined definitions that create less interferences (see Chap. 21). However, in this chapter, we will restrict ourselves to this definition and assume that two variables whose live ranges intersect cannot be assigned the same register.
- 2.
Hence, the terms “register” and “colour” will be used interchangeably in this chapter.
- 3.
- 4.
In a chordal graph, also called a triangulated graph, every cycle of length 4 or more has (at least) one chord (i.e., an edge joining two non-consecutive edges in the cycle).
- 5.
Observe that, with a program originally under SSA form, practical implementation may still choose to interleave the process of spilling and coalescing/colouring. Result will be unchanged, but speed might be impacted.
References
Berson, D. A., Gupta, R., & Soffa, M. L. (1999). Integrated instruction scheduling and register allocation techniques. In Proceedings of the International Workshop on Languages and Compilers for Parallel Computing. LCPC ’98 (pp. 247–262).
Bouchez, F., et al. (2006). Register allocation: What does the NP-completeness proof of chaitin et al. really prove? Or revisiting register allocation: Why and how. In Proceedings of the International Workshop on Languages and Compilers for Parallel Computing. LCPC ’06 (pp. 283–298).
Bouchez, F., Darte, A., & Rastello, F. (2008). Advanced conservative and optimistic register coalescing. In Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems. CASES ’08 (pp. 147–156).
Braun, M., Mallon, C., & Hack, S. (2010). Preference-guided register assignment. In International Conference on Compiler Construction. CC ’10 (pp. 205–223). New York: Springer.
Brisk, P., et al. (2005). Polynomial-time graph coloring register allocation. In International Workshop on Logic and Synthesis. IWLS ’05.
Chow, F., & Hennessy, J. L. (1990). The priority-based coloring approach to register allocation. ACM Transactions on Programming Language and Systems, 12(4), 501–536.
Codina, J. M., Sánchez, J., & González, A. (2001). A unified modulo scheduling and register allocation technique for clustered processors. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques. PACT ’01 (pp. 175–184).
Colombet, Q., et al. (2011). Graph-coloring and register allocation using repairing. In Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems. CASES ’04 (pp. 45–54).
Cytron, R. K., & Ferrante, J. (1987). What’s in a name? or the value of renaming for parallelism detection and storage allocation. In Proceedings of the 1987 International Conference on Parallel Processing (pp. 19–27).
Fabri, J. (1979). Automatic storage optimization. In SIGPLAN ’79.
Grund, D., & Hack, S. (2007). A fast cutting-plane algorithm for optimal coalescing. In International Conference on Compiler Construction. CC ’07 (pp. 111—125).
Hack, S., Grund, D., & Goos, G. (2005). Towards Register Allocation for Programs in SSA Form. Technical Report 2005–27. University of Karlsruhe.
Lueh, G.-Y., Gross, T., & Adl-Tabatabai, A.-R. (2000). Fusion-based register allocation. ACM Transactions on Programming Language and Systems, 22(3), 431–470 (2000).
Mössenböck, H., & Pfeiffer, M. (2002). Linear scan register allocation in the context of SSA form and register constraints. In International Conference on Compiler Construction. CC ’02 (pp. 229–246).
Motwani, R., et al. (1995). Combining Register Allocation and Instruction Scheduling. Technical Report. Stanford University.
Norris, C., & Pollock, L. L. (1993). A scheduler-sensitive global register allocator. In Proceedings of the International Conference on Supercomputing. ICS ’93 (pp. 804–813). New York: IEEE.
Park, J., & Moon, S.-M. (2004). Optimistic register coalescing. ACM Transactions on Programming Language and Systems, 26(4), 735–765.
Pereira, F. M. Q., & Palsberg, J. (2005). Register allocation via coloring of chordal graphs. In Asian Symposium on Programming Languages and Systems. APLAS ’05 (pp. 315–329).
Pinter, S. S. (1993). Register allocation with instruction scheduling. In International Conference on Programming Languages Design and Implementation. PLDI ’93 (pp. 248–257).
Rawat, P. S., et al. (2018). Register optimizations for stencils on GPUs. In Proceedings of the Symposium on Principles and Practice of Parallel Programming. PPoPP ’18 (pp. 168–182).
Sarkar, V., & Barik, R. (2007). Extended linear scan: an alternate foundation for global register allocation. In International Conference on Compiler Construction. CC ’07 (pp. 141–155). New York: Springer.
Smith, M. D., Ramsey, N., & Holloway, G. H. (2004). A generalized algorithm for graph-coloring register allocation. In International Conference on Programming Languages Design and Implementation. PLDI ’04 (pp. 277–288).
Tavares, A. L. C., et al. (2011). Decoupled graph-coloring register allocation with hierarchical aliasing. In Proceedings of the International Workshop on Software & Compilers for Embedded Systems. SCOPES ’11 (pp. 1–10).
Touati, S., & Eisenbeis, C. (2004). Early periodic register allocation on ILP processors. Parallel Processing Letters, 14(2), 287–313.
Wang, J., et al. (1994). Software pipelining with register allocation and spilling. In Proceedings of the International Symposium on Microarchitecture. MICRO 27 (pp. 95–99).
Wimmer, C., & Mössenböck, H. (2005). Optimized interval splitting in a linear scan register allocator. In Proceedings of the 1st ACM/USENIX International Conference on Virtual Execution Environments (pp. 132–141). Chicago: ACM.
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Tichadou, F.B., Rastello, F. (2022). Register Allocation. In: Rastello, F., Bouchez Tichadou, F. (eds) SSA-based Compiler Design. Springer, Cham. https://doi.org/10.1007/978-3-030-80515-9_22
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