Abstract
As electronic devices approach the sub 10-nm size and new device topologies emerge specifically exploiting quantum mechanical effects, new device simulation tools are needed addressing such issues. Among full quantum approaches, the k ⋅p model is known to provide a reasonably simple way to describe with good accuracy the complex system of valence and conduction bands of many semiconductors, including also their deformations induced by strain, which play a fundamental role in determining the electronic properties of the material. When used within the Non-Equilibrium Green’s Functions framework for the charge transport problem and coupled with Poisson’s equation, the k ⋅p model becomes a powerful tool for the simulation of full nanoelectronic devices featuring lateral confinement and quantum transport.
In this chapter, a review of the k ⋅p model is presented, with special emphasis on its applications to the simulation of nanoelectronic devices. The mathematical model of the so called eight-band version is duly recalled first, including the correction terms accounting for strain. Examples of energy band calculations are provided for III–V semiconductors, which are of great potential for the future development of the nanoelectronic industry, relative to both bulk and confined structures.
Significant examples of application of the k ⋅p model to full device simulation are then given, all of them relative to tunnel FETs. Specific topics include the investigation of strain in homojunction and heterojunction nanowire tunnel FETs, the optimization of complementary tunnel FETs and the evaluation of the performance of inverters built with the latter FETs, the investigation of the effect of interface traps on the same nanowire tunnel FETs.
The main idea that this chapter would like to convey is that in the next future there will most likely be an increasing type and number of nanoelectronic devices for which the k ⋅ p model represents a well targeted simulation basis.
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References
Luttinger, J.M., Kohn, W.: Motion of electrons and holes in perturbed periodic fields. Phys. Rev. 97(4) (1955)
E. O. Kane: Band structure of indium antimonide. J. Phys. Chem. Solids 1(4), 249–261 (1957)
Yu, P.Y., Cardona, D.M.: Fundamentals of Semiconductors, 4th edn. Springer, NewYork (2010)
Enderlein, R., Horing, N.J.M.: Fundamentals of Semiconductor Physics and Devices. World Scientific, Singapore (1997)
Chuang, S.L.: Physics of Optoelectronic Devices. Wiley, New York (1995)
Voon, L.C.L.Y., Willatzen, M.: The k ⋅ p Method. Springer, Berlin (2009)
Cardona, M., Pollak, F.H.: Energy-band structure of germanium and silicon: the k ⋅ p method. Phys. Rev. 142(2), 530 (1966)
Shin, M., Lee, S., Klimeck, G.: Computational study on the performance of si nanowire pMOSFETs based on the k⋅p method. IEEE Trans. Electron Devices 57(9) (2010)
Shin, M.: Full-quantum simulation of hole transport and band-to-band tunneling in nanowires using the k ⋅ p method. J. Appl. Phys. 106, 054505 (2009)
Baccarani, G., Baravelli, E., Gnani, E., Gnudi, A., Reggiani, S.: Theoretical analyses and modeling for nanoelectronics. In: Proc. of the ESSDERC/ESSCIRC Conference, pp. 4–9 (2015)
Esseni, D., Pala, M., Palestri, P., Alper, C., Rollo, T.: A review of selected topics in physics based modeling for tunnel field-effect transistors. Semicond. Sci. Technol. 32, 083005 (2017)
Selmi, L., Caruso, E., Carapezzi, S., Visciarelli, M., Gnani, E., Zagni, N., Pavan, P., Palestri, P., Esseni, D., Gnudi, A., Reggiani, S., Puglisi, F.M., Verzellesi, G.: Modelling nanoscale n-mosfets with III–V compound semiconductor channels: from advanced models for band structures, electrostatics and transport to tcad. In: Proc. of the IEDM Conference, pp. 322–325 (2017)
Vurgaftman, I., Meyer, J.R.: Elimination of spurious solutions from eight-band k⋅p theory. J. Appl. Phys. 89(11), 5815–5875 (2001)
Veprek, R.G., Steiger, S., Witzigmann, B.: Ellipticity and the spurious solution problem of k⋅p envelope equations. Phys. Rev. B 76(16), 165320 (2007)
Foreman, B.A.: Elimination of spurious solutions from eight-band k⋅p theory. Phys. Rev. B 56(20), R12748–R12751 (1997)
Bir, G.L., Pikus, G.E.: Symmetry and Strain-Induced Effects in Semiconductors. Wiley, NewYork (1974)
Bahder, T.B.: Eight-band k⋅p model of strained zinc-blende crystals. Phys. Rev. B 46(17), 11992–12001 (1990)
Bahder, T.B.: Erratum: Eight-band k⋅p model of strained zinc-blende crystals. Phys. Rev. B 46, 9913 (1992)
Chuang, S.L., Chang, C.S.: k-p method for strained wurtzite semiconductors. Phys. Rev. B 54, 2491–2504 (1996)
Pan, A., Chui, C.O.: Modeling direct interband tunneling: II. lower-dimensional structures. J. Appl. Phys. 116, 054509 (2014)
Caruso, E., Zerveas, G., Baccarani, G., Czornomaz, L., Daix, N., Esseni, D., Gnani, E., Gnudi, A., Grassi, R., Luisier, M., Markussen, T., Palestri, P., Schenk, A., Selmi, L., Sousa, M., Stokbro, K., Visciarelli, M.: Modeling approaches for band-structure calculation in III–V fet quantum wells. In: Proc. of the EUROSOI-ULIS Conference, pp. 101–104 (2015)
Rau, M., Markussen, T., Caruso, E., Esseni, D., Gnani, E., Gnudi, A., Khomyakov, P.A., Luisier, M., Osgnach, P., Palestri, P., Reggiani, S., Schenk, A., Selmi, L., Stokbro, K.: Performance study of strained III–V materials for ultra-thin body transistor applications. In: Proc. of the ESSDERC Conference, pp. 184–187 (2016)
Visciarelli, M., Gnani, E., Gnudi, A., Reggiani, S., Baccarani, G.: Impact of strain on tunneling current and threshold voltage in III-V nanowire TFETs. IEEE Electron Device Letters pp. 560–563 (2016)
Majumdar, K.: Band to band tunneling in III–V semiconductors: Implications of complex band structure, strain, orientation, and off-zone center contribution. J. Appl. Phys. 115(17), 174503 (2014)
Seabaugh, A., Zhang, Q.: Low-voltage tunnel transistors for beyond cmos logic. Proc. IEEE 98(12), 2095–2110 (2010)
Ionescu, A.M., Riel, H.: Tunnel field-effect transistors as energy efficient electronic switches. Nature 479(73), 329–337 (2011)
Pal, A., Sachid, A.B., Gossner, H., Rao, V.R.: Insights into the design and optimization of tunnel-fet devices and circuits. IEEE Trans. Electron Devices 58(4), 1045–1053 (2011)
Gnani, E., Gnudi, A., Reggiani, S., Baccarani, G.: Drain-conductance optimization in nanowire TFETs by means of a physics-based analytical model. Solid-State Electron. 84, 96–102 (2013)
Zhou, G., Li, R., Vasen, T., Qi, M., Chae, S., Lu, Y., Zhang, Q., Zhu, H., Kuo, J.M., Kosel, T., Wistey, M., Fay, P., Seabaugh, A., Xing, H.: Novel gate-recessed vertical InAs/GaSb TFETs with record high ION of 180 μA/μm at VDS = 0.5 V. In: Proc. of IEEE Int. IEDM Conference, p. 777–780 (2012)
Lake, R., Klimeck, G., R. C.B., Jovanovic, D.: Single and multiband modeling of quantum electron transport through layered semiconductor devices. J. Appl. Phys. 81(12), 7845–7869 (1997)
Luisier, M., Klimeck, G.: Performance comparisons of tunneling field-effect transistors made of insb, carbon, and gasb-inas broken gap heterostructures. In: Proc. of IEEE Int. IEDM Conference, p. 913–916 (2009)
Baravelli, E., Gnani, E., Grassi, R., Gnudi, A., Reggiani, S., Baccarani, G.: Optimization of n- and p-type tfets integrated on the same inas/alxga1-xsb technology platform. IEEE Trans. Electron Devices 61(1), 178–184 (2014)
Visciarelli, M., Gnani, E., Gnudi, A., Reggiani, S., Baccarani, G.: Design guidelines for gasb/inas tfet exploiting strain and device size. Solid-State Electron. pp. 157–162 (2017)
Gandhi, R., Chen, Z., Singh, N., Banerjee, K., Lee, S.: CMOS-compatible vertical-silicon-nanowire gate-all-around p-type tunneling FETs with ≤50-mV/decade subthreshold swing. IEEE Electron Device Lett. 32(11), 1504–1506 (2011)
Borg, M., Schmid, H., Moselund, K.E., Signorello, G., Gignac, L., Bruley, J., Breslin, C., Kanungo, P.D., Werner, P., Riel, H.: Vertical III–V nanowire device integration on si(100). Nano Lett. 14(4), 1914–1920 (2014)
Conzatti, F., Pala, M.G., Esseni, D., Bano, E., Selmi, L.: Strain induced performance improvements in inas nanowire tunnel fets. IEEE Trans. Electron Devices 59(8), 2085–2092 (2012)
International technology roadmap for semiconductors—2012. http://www.itrs.net/Links/2012ITRS/Home2012.htm
Conzatti, F., Pala, M.G., Esseni, D., Bano, E., Selmi, L.: A simulation study of strain induced performance enhancements in inas nanowire tunnel-fets. In: Proc. of IEEE Int. IEDM Conference, p. 5.2.1 (2011)
Conzatti, F., Pala, M.G., Esseni, D., Bano, E.: Investigation of localized versus uniform strain as a performance booster in inas tunnel-fets. Solid State Electron. 88, 49–53 (2013)
Visciarelli, M., Gnani, E., Gnudi, A., Reggiani, S., Baccarani, G.: Impact of traps and strain on optimized n- and p-type TFETs integrated on the same InAs/AlGaSb technology platform. IEEE Trans. Electron Devices 64(8), 3108–3113 (2017)
Knoch, J., Appenzeller, J.: Modeling of high-performance p-type III–V heterojunction tunnel fets. IEEE Electron Device Lett. 31(4), 305–307 (2010)
Baravelli, E., Gnani, E., Gnudi, A., Reggiani, S., Baccarani, G.: Tfet inverters on the same technology platform for low-voltage/low-power applications. IEEE Trans. Electron Devices 61(2), 473–478 (2014)
Mookerjea, S., Krishnan, R., Datta, S., Narayanan, V.: Effective capacitance and drive current for tunnel fet tfet CV/I estimation. IEEE Trans. Electron Devices 56(9), 2092–2098 (2009)
Sinha, S., Yeric, G., Chandra, V., Cline, B., Cao, Y.: Exploring sub-20 nm finfet design with predictive technology models. In: Proc. of DAC Conference, pp. 283–288 (2012)
Passlack, M., Droopad, R., Brammertz, G.: Suitability study of oxide/gallium arsenide interfaces for mosfet applications. IEEE Trans. Electron Devices 57(11), 2944–2956 (2010)
Lin, L., Robertson, J.: Defect states at III–V semiconductor oxide interfaces. Appl. Phys. Lett. 98(8), 082903 (2011)
Pala, M.G., Esseni, D., Conzatti, F.: Impact of interface traps on the IV curves of inas tunnel-fets and mosfets: a full quantum study. In: Proc. of IEEE Int. IEDM Conference, p. 6.6.1 (2012)
Visciarelli, M., Gnani, E., Gnudi, A., Reggiani, S.: A full-quantum simulation study of InGaAs NW MOSFETs including interface traps. In: Proc. of Eur. Solid-State Device Res. Conf. (ESSDERC), p. 180–183 (2016)
Wang, S.W., Vasen, T., Doornbos, G., Oxland, R., Chang, S.W., Li, X., Contreras-Guerrero, R., Holland, M., Wang, C.H., Edirisooriya, M., S.R.R., Ramvall, J.P., Thoms, S., VeUianitis, M.D.G., Hsien, G.C.H., Chang, Y.S., K.M.Y., Yeo, Y.C., C.H.D., Droopad, R., I.G.T., Passlack, M.: Field-effect mobility of inas surface channel nmosfet with low d it scaled gate stack. IEEE Trans. Electron Devices 62(8), 2429–2436 (2015)
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Gnudi, A., Gnani, E., Reggiani, S., Baccarani, G. (2023). Application of the k ⋅ p Method to Device Simulation. In: Rudan, M., Brunetti, R., Reggiani, S. (eds) Springer Handbook of Semiconductor Devices . Springer Handbooks. Springer, Cham. https://doi.org/10.1007/978-3-030-79827-7_41
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