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Generation and Verification of Timing Attack Resilient Schedules During the High-Level Synthesis of Integrated Circuits

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Behavioral Synthesis for Hardware Security

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Abstract

Variabilities in the execution time of integrated circuits enable side-channel attacks that expose secret embedded information of deployed computer systems and circuits. Typical countermeasures rely on analysis and modification of the explicit timing behavior in lower level hardware description languages, which is time consuming and error-prone. In this chapter we investigate the integration of timing attack resilience into the high-level synthesis (HLS) of integrated circuits. HLS translates programs expressed in higher-level programming languages, such as C, to synthesizable hardware. Our approach applies timing annotations of basic blocks in C to add scheduling constraints that balance the execution time of security-related execution branches during the synthesis process. We formally validate the timing invariance of the integrated circuit by encoding the resulting schedule as a bounded model checking satisfiability problem. We integrate our approach to the scheduling of the open source LegUp HLS tool and apply the proposed method for the asymmetric cryptography algorithms RSA and ECC. The results proof the resistance against timing attacks, with a negligible overhead in synthesis efforts, area, and run-time.

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Authors and Affiliations

  1. Center for Embedded Systems and Cyber-Physical Systems (CECS), University of California, Irvine, CA, USA

    Steffen Peter & Tony Givargis

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  1. Steffen Peter
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  2. Tony Givargis
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Correspondence to Tony Givargis .

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Editors and Affiliations

  1. Department of Computer Science and Engineering, University of South Florida, Tampa, FL, USA

    Srinivas Katkoori

  2. Department of Computer Science, University of Texas Rio Grande Valley, Edinburg, TX, USA

    Sheikh Ariful Islam

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Peter, S., Givargis, T. (2022). Generation and Verification of Timing Attack Resilient Schedules During the High-Level Synthesis of Integrated Circuits. In: Katkoori, S., Islam, S.A. (eds) Behavioral Synthesis for Hardware Security. Springer, Cham. https://doi.org/10.1007/978-3-030-78841-4_15

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  • DOI: https://doi.org/10.1007/978-3-030-78841-4_15

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-78840-7

  • Online ISBN: 978-3-030-78841-4

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