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Defense Against Hardware Trojan Collusion in MPSoCs

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Behavioral Synthesis for Hardware Security
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Abstract

This chapter introduces a method aiming to mute or detect hardware Trojan collusion in a multiprocessor system-on-chip (MPSoC). Hardware Trojans—malicious hardware modifications—in untrusted third-party IP (3PIP) processors may collude with each other, causing system-wide catastrophe. To prevent this, the method described in this chapter integrates “design-for-trust” (DfT) and “runtime monitoring”. First of all, the threat model of hardware Trojan collusion in MPSoCs will be given. Then, the motivation of utilizing IP vendor diversity as one of the DfT techniques will be discussed, followed by another DfT technique—security-aware task scheduling with a set of new security rules. An Integer Linear Programming (ILP) model and two heuristics are presented to ensure that the introduced security constraints can be fulfilled with minimum impact on other design goals, such as performance and hardware cost. As only communication channels between different vendors are considered “safe” and used to convey authorized inter-task communications, at runtime, unauthorized communications will either be muted if they are on a safe channel, or be detected if they are on an unsafe channel. The chapter concludes with experimental results that evaluate the effectiveness and efficiency of the proposed security enhancement.

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Notes

  1. 1.

    It is assumed that the scheduling is non-preemptive, that is, a task in execution cannot be preempted by any other task.

  2. 2.

    This assumption can be easily extended to model different cores from one vendor.

  3. 3.

    Graph coloring [8] is the problem of finding the minimum number of colors that ensure adjacent vertices in a graph do not share the same color.

  4. 4.

    The definitions of V , C, and E hold for the remaining algorithms as well.

  5. 5.

    The maximum clique of a graph is its largest complete subgraph . A graph with a maximum clique size of k needs at least k colors to color it.

  6. 6.

    If no edge is added, the maximum clique size does not change.

  7. 7.

    In MSI, each cache block can have one of three possible states: Modified, Shared, and Invalid. More details about the protocol can be found in [13].

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Liu, C., Yang, C. (2022). Defense Against Hardware Trojan Collusion in MPSoCs. In: Katkoori, S., Islam, S.A. (eds) Behavioral Synthesis for Hardware Security. Springer, Cham. https://doi.org/10.1007/978-3-030-78841-4_11

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  • DOI: https://doi.org/10.1007/978-3-030-78841-4_11

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  • Online ISBN: 978-3-030-78841-4

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