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Hardware Trojan Localization: Modeling and Empirical Approach

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Behavioral Synthesis for Hardware Security

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Abstract

This chapter presents mechanisms to localize Hardware Trojan (HT) in modern Integrated Circuit (IC) supply chain to ensure trustworthiness of computing infrastructure. We employ both analytical and estimation techniques to validate the localization. Our estimation framework is built upon characterizing technology mapped arithmetic module architectures. Such analysis does not require any golden design while simultaneously raises the abstraction to Register-Transfer Level (RTL). We present an analytical modeling technique that can identify rare activity region and complement traditional testing-based detection mechanism. Our experimental evaluation has been conducted on six adders and four multiplier architectures. On average, we observe less than 2% Mean Square Error (MSE) as we evaluate the architectures of different bit-width and correlations.

This work was done as part of the first author’s dissertation research at USF.

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Authors and Affiliations

  1. University of Texas Rio Grande Valley, Edinburg, TX, USA

    Sheikh Ariful Islam

  2. University of South Florida, Tampa, FL, USA

    Srinivas Katkoori

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  1. Sheikh Ariful Islam
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Correspondence to Sheikh Ariful Islam .

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Editors and Affiliations

  1. Department of Computer Science and Engineering, University of South Florida, Tampa, FL, USA

    Srinivas Katkoori

  2. Department of Computer Science, University of Texas Rio Grande Valley, Edinburg, TX, USA

    Sheikh Ariful Islam

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Islam, S.A., Katkoori, S. (2022). Hardware Trojan Localization: Modeling and Empirical Approach. In: Katkoori, S., Islam, S.A. (eds) Behavioral Synthesis for Hardware Security. Springer, Cham. https://doi.org/10.1007/978-3-030-78841-4_10

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  • DOI: https://doi.org/10.1007/978-3-030-78841-4_10

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