Abstract
Nowadays, Traditional parallel communication cannot meet the standard for high-speed links for inter-Integrated Circuits (IC) data transmission. On-Chip SerDes Transceiver is a promising solution which can reduce the number of interconnects and offers remarkable benefits in context with power consumption, area congestion and crosstalk. This article presents a description of the design of Low-Power High-Speed On-Chip 5 to 1 Serializer architecture in 180 nm Technology that is used to perform the data serialization function in a SerDes system. This architecture is designed with a clock frequency of 160 MHz and the overall power consumption is estimated as 2.02 mW. The proposed serializer was designed and simulated in Cadence using TSMC 180 nm technology with a supply voltage of 1.8 V.
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Menssouri, A., El Khadiri, K., Qjidaa, H., Lakhssassi, A., Tahiri, A. (2021). Low-Power High-Speed On-Chip 5 to 1 Serializer in 180 nm Technology. In: Motahhir, S., Bossoufi, B. (eds) Digital Technologies and Applications. ICDTA 2021. Lecture Notes in Networks and Systems, vol 211. Springer, Cham. https://doi.org/10.1007/978-3-030-73882-2_148
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DOI: https://doi.org/10.1007/978-3-030-73882-2_148
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Online ISBN: 978-3-030-73882-2
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