Abstract
The wire probe-and-fault models are currently the most used models to provide arguments for side-channel and fault security. However, several practical attacks are not yet covered by these models. This work extends the wire fault model to include more advanced faults such as area faults and permanent faults. Moreover, we show the tile probe-and-fault adversary model from CRYPTO 2018’s CAPA envelops the extended wire fault model along with known extensions to the probing model such as glitches, transitions, and couplings. In other words, tiled (tessellated ) designs offer security guarantees even against advanced probe and fault adversaries.
As tiled models use multi-party computation techniques, countermeasures are typically expensive for software/hardware. This work investigates a tiled countermeasure based on the ISW methodology which is shown to perform significantly better than CAPA for practical parameters.
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Notes
- 1.
On hardware this functionality is replaced by a specialised mechanism such as a cascading gadget from the work by Ishai et al. [18].
- 2.
A connection between the security of parallel operations and the probing security of sequential operations is discussed in the work by Barthe et al. [2].
- 3.
The \(d+1\) RNGs can be replaced by a \(d^{th}\)-order tiled secure RNG if this is available.
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Acknowledgements
We thank François-Xavier Standaert and Gaëtan Cassiers for the interesting discussions. Siemen Dhooghe is supported by a PhD Fellowship from the Research Foundation – Flanders (FWO). Svetla Nikova was partially supported by the Bulgarian National Science Fund, Contract No. 12/8
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Dhooghe, S., Nikova, S. (2021). Let’s Tessellate: Tiling for Security Against Advanced Probe and Fault Adversaries. In: Liardet, PY., Mentens, N. (eds) Smart Card Research and Advanced Applications. CARDIS 2020. Lecture Notes in Computer Science(), vol 12609. Springer, Cham. https://doi.org/10.1007/978-3-030-68487-7_12
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