Abstract
The article describes results of our research of hardware implementation efficiency of sorting algorithms created by using of Xilinx’s High-Level Synthesis tools, the Vivado HLS package, and FPGAs. The term efficiency, used in the research, defined as a function of the performance, estimated in time for sorting a random generated array, and hardware “cost”, estimated in utilized FPGA resources. In the research, a simulation modeling and a comparative analysis was carried out for the wide range of sorting algorithms implemented on a universal processor and on the Xilinx’s FPGAs. The research results prove that hardware implementations of the sorting algorithms, synthesized by Xilinx HLS tool, do not always provide higher performance comparing with the implementations of the same algorithms on a universal processor. The article shows that the hardware implementation of the Merge sort algorithm, created by Xilinx’s HLS tool, can speed up, comparing with software implementation, the process of sorting arrays of small and medium size.
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References
Antonov, A., Zaborovskij, V., Kalyaev, I.: The architecture of a reconfigurable heterogeneous distributed supercomputer system for solving the problems of intelligent data processing in the era of digital transformation of the economy. Cybersecur. Issues 33(5), 2–11 (2019). https://doi.org/10.21681/2311-3456-2019-5-02-11
Mantovani, F., Calore, E.: Performance and power analysis of HPC workloads on heterogeneous multi-node clusters. Low Power Electron. Appl. 8(2), 13–27 (2018). https://doi.org/10.3390/jlpea8020013
Usman Ashraf, M., Alburaei Eassa, F., Ahmad Albeshri, A., Algarni, A.: Performance and power efficient massive parallel computational model for HPC heterogeneous exascale systems. IEEE Access 6, 23095–23107 (2018). https://doi.org/10.1109/ACCESS.2018.2823299
Kobayashi, R., Oobata, Y., Fujita, N., Yamaguchi, Y., Boku, T.: OpenCL-ready high speed FPGA network for reconfigurable high performance computing, In: Proceedings of International Conference on High Performance Computing in Asia-Pacific, HPC Asia, pp. 192–201 (2018). https://doi.org/10.1145/3149457.3149479
Antonov, A., Zaborovskij, V., Kisilev, I.: Specialized reconfigurable computers in network-centric supercomputer systems. High Availab. Syst. 14(3), 57–62 (2018). https://doi.org/10.18127/j20729472-201803-09
Dongarra, J., Gottlieb, S., Kramer, W.: Race to exascale. Comput. Sci. Eng. 21(1), 4–5 (2019). https://doi.org/10.1109/MCSE.2018.2882574
Haidar, A., Jagode, H., Vaccaro, P., YarKhan, A., Tomov, S., Dongarra, J.: Investigating power capping toward energy-efficient scientific applications. Concurr. Comput. Pract. Exp. 1–14 (2018). https://doi.org/10.1002/cpe.4485
Le Fèvre, V., Herault, T., Robert, Y., Bouteiller, A., Hori, A., Bosilca, J.G., Dongarra, J.: Comparing the performance of rigid, moldable and grid-shaped applications on failure-prone HPC platforms. Parallel Comput. 85, 1–12 (2019). https://doi.org/10.1016/j.parco.2019.02.002
IDE Vivado HLS. https://www.xilinx.com/video/hardware/vivado-hls-tool-overview.html. Accessed 19 April 2020
Intel HLS compiler. https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/hls-compiler.html?wapkw=HLS. Accessed 19 April 2020
Catapult HLS. https://www.mentor.com/hls-lp/catapult-high-level-synthesis/. Accessed 19 April 2020
Angermeier, J., Sibirko, E., Wanka, R., Teich, J.: Bitonic sorting on dynamically reconfigurable architectures. In: 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum, Shanghai, pp. 314–317, (2011). https://doi.org/10.1109/ipdps.2011.164
Mihhailov, D., Sklyarov, V., Skliarova I., Sudnitson, A.: Parallel FPGA-based implementation of recursive sorting algorithms, In: 2010 International Conference on Reconfigurable Computing and FPGAs, Quintana Roo, pp. 121–126, (2010). https://doi.org/10.1109/reconfig.2010.30
Janarbek M.I., et al.: Resolve: generation of high-performance sorting architectures from high-level synthesis. In: Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA ’16), pp. 195–204, New York, NY, USA (2016). https://doi.org/10.1145/2847263.2847268
Sorting Methods. https://www.mathworks.com/matlabcentral/fileexchange/45125-sorting-methods?focused=3805900&tab=function. Accessed 19 April 2020
Vitis_Libraries. https://github.com/Xilinx/Vitis_Libraries. Accessed 19 April 2020
Comb sort. https://www.geeksforgeeks.org/comb-sort/. Accessed 19 April 2020
Gnome sort. http://rosettacode.org/wiki/Sorting_algorithms/Gnome_sort. Accessed 19 April 2020
Merge sort. http://rosettacode.org/wiki/Sorting_algorithms/Merge_sort. Accessed 19 April 2020
Heap sort. http://rosettacode.org/wiki/Sorting_algorithms/Heapsort. Accessed 19 April 2020
Binary tree. https://www.geeksforgeeks.org/counting-sort/. Accessed 19 April 2020
Bucket sort, Web: https://en.wikipedia.org/wiki/Bucket_sort. Accessed 19 April 2020
Counting sort. https://www.geeksforgeeks.org/counting-sort/. Accessed 19 April 2020
Bictonic sorter. https://en.wikipedia.org/wiki/Bitonic_sorter. Accessed 19 April 2020
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The reported study was funded by RFBR, project number 18-29-03250.
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Antonov, A., Besedin, D., Filippov, A. (2020). Research of Hardware Implementations Efficiency of Sorting Algorithms Created by Using Xilinx’s High-Level Synthesis Tool. In: Voevodin, V., Sobolev, S. (eds) Supercomputing. RuSCDays 2020. Communications in Computer and Information Science, vol 1331. Springer, Cham. https://doi.org/10.1007/978-3-030-64616-5_39
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