Abstract
With the development of deep learning, the traditional neural networks architecture has been gradually met the bottleneck of the performance. Convolutional neural networks (CNNs) has been widely concerned because of its high precision advantage. However, CNNs are usually computationally large. And in addition to the widely used GPUs, but which has higher energy. And FPGA is gradually used to achieve CNNs acceleration due to its high performance, high concurrency, fast development cycle and re-configurability characteristics. Although previous works have made considerable progress, few researches have been used to address data dependence in data structure of CNN. Data dependence greatly affects the performance of accelerators. In this paper, we present a way to greatly improve the read efficiency of the accelerated hardware by reconstructing the original digital set and using the preload mechanism. This effectively reduces the problem of data dependence. In this way, pipeline technology can speed up the CNN computing process more effectively. We implemented the accelerator architecture on the XC 7z045 board, and the proposed accelerator has a clear advantage over previous studies to improve the efficiency and processing speed of CNNs.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
LeCun, Y., Bottou, L., Bengio, Y., Haffner, P.: Gradient-based learning applied to document recognition. Proc. IEEE 86(11), 2278–2324 (1998)
Krizhevsky, A., Sutskever, I., Hinton, G.E.: Imagenet classification with deep convolutional neural networks. In: Advances in Neural Information Processing Systems, pp. 1097–1105 (2012)
Zhang, Y., Pezeshki, M., Brakel, P., Zhang, S., Bengio, C.L.Y., Courville, A.: Towards end-to-end speech recognition with deep convolutional neural networks. arXiv preprint arXiv:1701.02720 (2017)
Liu, Wei., et al.: SSD: single shot multibox detector. In: Leibe, Bastian, Matas, Jiri, Sebe, Nicu, Welling, Max (eds.) ECCV 2016. LNCS, vol. 9905, pp. 21–37. Springer, Cham (2016). https://doi.org/10.1007/978-3-319-46448-0_2
Szegedy, C., et al.: Going deeper with convolutions. In: Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, pp. 1–9 (2015)
Li, H., Fan, X., Jiao, L., Cao, W., Zhou, X., Wang, L.: A high performance FPGA-based accelerator for large-scale convolutional neural networks. In: 2016 26th International Conference on Field Programmable Logic and Applications (FPL), pp. 1–9. IEEE (2016)
Suda, N., et al.: Throughput-optimized OpenCL-based FPGA accelerator for large-scale convolutional neural networks. In: Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 16–25 (2016)
Maki, A., Miyashita, D., Nakata, K., Tachibana, F., Suzuki, T., Deguchi, J.: Fpga-based cnn processor with filter-wise-optimized bit precision. In: 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 47–50. IEEE (2018)
Peemen, M., Setio, A.A.A., Mesman, B., Corporaal, H.: Memory-centric accelerator design for convolutional neural networks. In: 2013 IEEE 31st International Conference on Computer Design (ICCD), pp. 13–19. IEEE (2013)
Zhang, C., Li, P., Sun, G., Guan, Y., Xiao, B., Cong, J.: Optimizing fpga-based accelerator design for deep convolutional neural networks. In: Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 161–170 (2015)
Li, Y., Liu, Z., Xu, K., Yu, H., Ren, F.: A 7.663-TOPS 8.2-W energy-efficient FPGA accelerator for binary convolutional neural networks. In: FPGA, pp. 290–291 (2017)
Zhang, C., Wu, D., Sun, J., Sun, G., Luo, G., Cong, J.: Energy-efficient CNN implementation on a deeply pipelined FPGA cluster. In: Proceedings of the 2016 International Symposium on Low Power Electronics and Design, pp. 326–331 (2016)
Lu, L., Liang, Y., Xiao, Q., Yan, S.: Evaluating fast algorithms for convolutional neural networks on FPGAs. In: 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp 101–108. IEEE (2017)
Yang, Y., et al.: Synetgy: algorithm-hardware co-design for convnet accelerators on embedded fpgas. In: Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 23–32 (2019)
Gschwend, D.: ZynqNet: an FPGA-accelerated embedded convolutional neural network. ETH Zurich (2016)
Hu. W, Chen. S, Li, Z.-H., Liu, T.-Y., Li, Y.-N.: Data optimization CNN accelerator design on FPGA. In: 2019 IEEE International Conference on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom), pp. 294–299. IEEE (2019)
LeCun, Y., et al.: Gradient-based learning applied to document recognition. Proc. IEEE 86(11), 2278–2324 (1998)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2020 Springer Nature Switzerland AG
About this paper
Cite this paper
Dong, Y., Hu, W., Wang, Y., Jiao, Q., Chen, S. (2020). Optimizing Accelerator on FPGA for Deep Convolutional Neural Networks. In: Qiu, M. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2020. Lecture Notes in Computer Science(), vol 12453. Springer, Cham. https://doi.org/10.1007/978-3-030-60239-0_7
Download citation
DOI: https://doi.org/10.1007/978-3-030-60239-0_7
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-60238-3
Online ISBN: 978-3-030-60239-0
eBook Packages: Mathematics and StatisticsMathematics and Statistics (R0)