Abstract
Embedded image processing systems face stringent and conflicting constraints which commonly result in developers overly specialising systems to the problem-at-hand. In other words, they give priority to efficiency, which is an immediate concern, over the longer term development cost reduction benefits of building reusable components. In this paper, we present the foundational Tulipp Reference Platform (TRP) which enables making domain-specific generality versus specificity trade-offs through the definition of TRP instances. Each TRP instance includes the key software and hardware components for a given domain as well as productivity-enhancing components if these can be accommodated within the typical constraints of the domain. While TRP instances primarily enable intra-domain reuse, they also enable inter-domain reuse as collections of components used in one instance may be straightforwardly reused in other instances. At present, TRP instances are defined for the space, medical, automotive, robotics, and Unmanned Aerial Vehicle (UAV) domains.
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References
Bacon, D.F., Rabbah, R., Shukla, S.: FPGA programming for the masses. Commun. ACM 56(4), 56–63 (2013)
Bialas, P., Strzelecki, A.: Benchmarking the cost of thread divergence in CUDA. arXiv:1504.01650 [cs] (2015). http://arxiv.org/abs/1504.01650
Canis, A., Choi, J., Aldham, M., Zhang, V., Kammoona, A., Czajkowski, T., Brown, S.D., Anderson, J.H.: LegUp: An Open-source High-level Synthesis Tool for FPGA-based Processor/Accelerator Systems. ACM Trans. Embed. Comput. Syst. 13(2), 24:1–24:27 (2013)
Horowitz, M., Indermaur, T., Gonzalez, R.: Low-power digital design. In: Symposium on Low Power Electronics, pp. 8–11 (1994)
Jahre, M., Eeckhout, L.: GDP: Using dataflow properties to accurately estimate interference-free performance at runtime. In: International Symposium on High Performance Computer Architecture (HPCA), pp. 296–309 (2018)
Jahre, M., Grannaes, M., Natvig, L.: A quantitative study of memory system interference in chip multiprocessor architectures. In: Proceedings of the International Conference on High Performance Computing and Communications (HPCC) (2009)
Jahre, M., Natvig, L.: A high performance adaptive miss handling architecture for chip multiprocessors. Trans. High Perform. Embed. Archit. Compil. 4(1) (2009)
Kalb, T., Kalms, L., Göhringer, D., Pons, C., Marty, F., Muddukrishna, A., Jahre, M., Kjeldsberg, P.G., Ruf, B., Schuchert, T., Tchouchenkov, I., Ehrenstrahle, C., Christensen, F., Paolillo, A., Lemer, C., Bernard, G., Duhem, F., Millet, P.: TULIPP: Towards ubiquitous low-power image processing platforms. In: Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), pp. 306–311 (2016)
Koraei, M., Fatemi, O., Jahre, M.: DCMI: A scalable strategy for accelerating iterative stencil loops on FPGAs. ACM Trans. Archit. Code Optim. 16(4), 36:1–36:24 (2019)
Krishnan, S., Borojerdian, B., Fu, W., Faust, A., Reddi, V.J.: Air Learning: An AI research platform for algorithm-hardware benchmarking of autonomous aerial robots. arXiv:1906.00421 [cs] (2019). http://arxi.org/abs/1906.00421
Kruger, J., Dunning, D.: Unskilled and unaware of it: How difficulties in recognizing one’s own incompetence lead to inflated self-assessments. J. Pers. Soc. Psychol. 77(6), 1121 (1999)
Liu, Y., Zhao, X., Jahre, M., Wang, Z., Wang, X., Luo, Y., Eeckhout, L.: Get out of the valley: Power-efficient address mapping for GPUs. In: Proceedings of the International Symposium on Computer Architecture (ISCA) (2018)
NVIDIA: CUDA C++ Programming Guide. Tech. rep. (2019)
Open Robotics: Robot Operating System (ROS). https://www.ros.org/ (2020)
Qasaimeh, M., Denolf, K., Lo, J., Vissers, K., Zambreno, J., Jones, P.H.: Comparing energy efficiency of CPU, GPU and FPGA implementations for vision kernels. In: Proceedings of the International Conference on Embedded Software and Systems (ICESS) (2019)
Reissmann, N., Falch, T.L., Bjørnseth, B.A., Bahmann, H., Meyer, J.C., Jahre, M.: Efficient control flow restructuring for GPUs. In: International Conference on High Performance Computing Simulation (HPCS), pp. 48–57 (2016)
Ruf, B.: Guideline 26: Use conditional branching carefully. https://github.com/tulipp-eu/tulipp-guidelines/wiki/Use-conditional-branching-carefully (2019)
Sharifian, A., Hojabr, R., Rahimi, N., Liu, S., Guha, A., Nowatzki, T., Shriraman, A.: uIR - An intermediate representation for transforming and optimizing the microarchitecture of application accelerators. In: Proceedings of the International Symposium on Microarchitecture (MICRO) (2019)
Tulipp: Tulipp guidelines. https://github.com/tulipp-eu/tulipp-guidelines/wiki (2019)
Umuroglu, Y., Fraser, N.J., Gambardella, G., Blott, M., Leong, P., Jahre, M., Vissers, K.: FINN: A framework for fast, scalable binarized neural network inference. In: Proceedings of the International Symposium on Field-Programmable Gate Arrays (FPGA), pp. 65–74 (2017)
Umuroglu, Y., Jahre, M.: An energy efficient column-major backend for FPGA SpMV accelerators. In: Proceedings of the International Conference on Computer Design (ICCD), pp. 432–439 (2014)
Xilinx: Vivado High-Level Synthesis (2018). URL https://www.xilinx.com/products/design-tools/vivado/integration/esl-design.html
Acknowledgements
We would like to thank Ananya Muddukrishna for his contributions to the initial formulation of the guidelines concept. This work has been funded in part by the European Horizon 2020 project Tulipp (grant agreement #688403).
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Jahre, M., Millet, P. (2021). TRP: A Foundational Platform for High-Performance Low-Power Embedded Image Processing. In: Jahre, M., Göhringer, D., Millet, P. (eds) Towards Ubiquitous Low-power Image Processing Platforms . Springer, Cham. https://doi.org/10.1007/978-3-030-53532-2_2
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DOI: https://doi.org/10.1007/978-3-030-53532-2_2
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