Abstract
The Keccak permutation function constitutes the essential part of the computations in the SHA-3 (Secure Hash Algorithm-3) standard. Its fast implementation in hardware is crucial for efficient operation of many contemporary ICT systems which commonly apply hashing e.g. in data storage and transmission or in security protection. This paper analyzes potential improvements in computation speed of the function if its hardware implementation uses a pipelined organization where the single Keccak round is divided into two or three pipeline stages. The discussion starts with examination of various options for such pipelining and then the proposed architectures are implemented in a Spartan-7 FPGA device from Xilinx. Estimations of their maximum frequencies of operation illustrate speed gains (in terms of total throughput) which can be accomplished by the increased parallelization achieved through fine-grained pipelining. The results indicate that after careful tuning of the overall control framework the complete module calculating the 1600-bit permutation can operate at frequencies exceeding 500 MHz even in a device from this economy-grade FPGA family.
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Sugier, J. (2020). Intra-round Pipelining of Keccak Permutation Function in FPGA Implementations. In: Zamojski, W., Mazurkiewicz, J., Sugier, J., Walkowiak, T., Kacprzyk, J. (eds) Theory and Applications of Dependable Computer Systems. DepCoS-RELCOMEX 2020. Advances in Intelligent Systems and Computing, vol 1173. Springer, Cham. https://doi.org/10.1007/978-3-030-48256-5_59
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DOI: https://doi.org/10.1007/978-3-030-48256-5_59
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