Abstract
The yield of an Integrated Circuit (IC) is commonly expressed as the fraction (in %) of working chips overall manufactured chips and often interpreted as the failure probability of its analog blocks. We consider the Importance Sampling Monte Carlo (ISMC) as a reference method for estimating failure probabilities. For situations where only a limited number of simulations is allowed, ISMC remains unattractive. In such cases, we propose an unbiased hybrid Monte Carlo approach that provides a fast estimation of the probability. Hereby we use a combination of a surrogate model, ISMC technique and the stratified sampling.
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Notes
- 1.
The approach can be extended for other distributions assuming that the original input distributions can be transformed into a standard Gaussian distribution.
- 2.
Surrogate models mimic the complex behaviour of (circuit) simulation model. The study of surrogate models is out of scope of this paper. A review on surrogate models is given in [3].
- 3.
An allocation means the partition of N.
- 4.
We keep sampling from g(x) until we have N i accepted samples.
- 5.
- 6.
In theory, the reference probability is the true failure probability to which the simulated results to be compared. However, in practice, we do not know the true probability. Thus, an approximation (with a high accuracy) of the true probability is used.
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Acknowledgement
The first author is grateful to the financial support from the Marie Curie Action.
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Tyagi, A.K., Jonsson, X., Beelen, T., Schilders, W.H.A. (2020). An Unbiased Hybrid Importance Sampling Monte Carlo Approach for Yield Estimation in Electronic Circuit Design. In: Nicosia, G., Romano, V. (eds) Scientific Computing in Electrical Engineering. SCEE 2018. Mathematics in Industry(), vol 32. Springer, Cham. https://doi.org/10.1007/978-3-030-44101-2_22
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DOI: https://doi.org/10.1007/978-3-030-44101-2_22
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