Abstract
A research on VLSI Floor planning’s physical layout is addressed using optimization methods to improve VLSI chip efficiency. VLSI floor planning is regarded as a non-polynomial issue. Calculations can solve such issues. Representation of floorplan is the basis of this process. The depictions of the floor plan demonstrate more effect on search space as well as the design complexity of the floor plan. This article aims at exploring various algorithms which add to the issue of managing alignment limitations such as excellent positioning, optimal region and brief run time. Many scientists are proposing and suggesting diverse heuristic algorithms and also distinct metaheuristic algorithms to solve the VLSI Floor plan issue. Simulated Annealing, tab search, ant colony optimization algorithm at last the genetic optimization algorithm are addressed in this article.
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References
Kahng, A.B., Lienig, J., Markov, I.L., Hu, J.: VLSI Physical Design: From Graph Partitioning to Timing Closure. Springer, New York (2011)
Van Laarhoven, P.J.M., Aarts, E.H.: Simulated annealing. Theory and Applications (1987); Dorigo, M., Caro, G.D., Gambardella, L.M.: Ant algorithms for discrete optimization. Artif. Life 5(2), 137–72 (1999)
Ninomiya, H., Numayama, K., Asai, H.: Two-staged tabu search for floorplan problem using o-tree representation. In: Proceedings of IEEE Congress on Evolutionary Computation, Vancouver (2006)
CordĂłn GarcĂa, O., Herrera Triguero, F., StĂĽtzle, T.: A review on an colony optimization meta-heuristic: basis, models and new trends (2002)
Sivasubramanian, K., Jayanthi, K.B.: Voltage-island based floorplanning in VLSI for area minimization using meta-heuristic optimization algorithm. Int. J. Appl. Eng. Res. 11(5), 3469–3477 (2016). ISSN: 0973-4562
Premalatha, B., Umamaheswari, D.S.: Attractive and repulsive particle swarm optimization algorithm based wire length minimization in FPGA placement. Int. J. VLSI Des. Commun. Syst. 03 (2015)
Shanavas, I.H., Gnanamurthy, R.K.: Optimal solution for VLSI physical design automation using hybrid genetic algorithm. Hindawi Publ. Corp. Math. Probl. Eng. 2014
Chen, X., Hu, J., Xu, N.: Regularity-constrained floorplanning for multi-core processors. Integr. VLSI J. 47, 86–95 (2014)
Abdullah, D.M., Abdullah, W.M., Babu, N.M., Bhuiyan, M.M.I., Nabi, K.M., Rahman, M.S.: VLSI floorplanning design using clonal selection algorithm. Int. Conf. Inform. Electron. Vis. (ICIEV) (2013)
Gracia, N.R.D., Rajaram, S.: Analysis and design of VLSI Floorplanning algorithms for nano-circuits. Int. J. Adv. Eng. Technol. (2013)
Sivaranjani, P., Kawya, K.K.: Performance analysis of VLSI floor-planning using evolutionary algorithm. Int. J. Comput. Appl. 0975–8887 (2013)
Singha, T., Dutta, H.S., De, M.: Optimization of floor-planning using genetic algorithm. Procedia Technol. 4, 825–829 (2012)
Hoyingcharoen, P., Teerapabkajorndet, W.: Fault tolerant sensor placement optimization with minimum detection probability guaranteed. In: 8th International Workshop on the Design of Reliable Communication Networks (DRCN) (2011)
Sheng, Y., Takahashi, A., Ueno, S.: RRA-based multi-objective optimization to mitigate the worst cases of placement. In: IEEE 9th International Conference on ASIC (ASICON) (2011)
Chen, J., Zhu, W.: A hybrid genetic algorithm for VLSI floorplanning. In: IEEE International Conference on Intelligent Computing and Intelligent Systems (ICIS) (2010)
Chen, G., Guo, W., Cheng, H., Fen, X., Fang, X.: VLSI Floor planning based on particle swarm optimization. In: 3rd International Conference on Intelligent System and Knowledge Engineering (2008)
Kilaru, S., Harikishore, K., Sravani, T., Chowdary, A., Balaji, T.: Review and analysis of promising technologies with respect to fifth generation networks. In: 1st International Conference on Networks and Soft Computing. (2014). ISSN: 978-1-4799-3486-
Gopal, P.B., Kishore, K.H. and Kittu, B.P.: An FPGA implementation of on chip UART testing with BIST techniques. Int. J. Appl. Eng. Res. 10(14), 34047–34051 (2015). ISSN: 0973-4562
Hussain, S.N., Kishore, K.H.: Computational optimization of placement and routing using genetic algorithm. Indian J. Sci. Technol. 9(47), 1–4, (2016). ISSN: 0974-6846
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Nazeer Hussain, S., Hari Kishore, K. (2020). Heuristic Approach to Evaluate the Performance of Optimization Algorithms in VLSI Floor Planning for ASIC Design. In: Gunjan, V., Zurada, J., Raman, B., Gangadharan, G. (eds) Modern Approaches in Machine Learning and Cognitive Science: A Walkthrough. Studies in Computational Intelligence, vol 885 . Springer, Cham. https://doi.org/10.1007/978-3-030-38445-6_16
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DOI: https://doi.org/10.1007/978-3-030-38445-6_16
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