Abstract
This paper examines efficiency of hardware realizations of DES cracking engines implemented in contemporary low-cost Spartan-7 devices from Xilinx, Inc. The engines are designed for the known plaintext attack scheme and find the secret cipher key through brute-force exhaustive search of the entire key space. In order to comprehensively evaluate potential of the selected FPGA family in this task three architectures of DES decoders were tested: the standard iterative organization, the fully unrolled i.e. purely combinational one and the fully unrolled pipelined version. Various sizes of individual decipher units based on these three architectures led to evaluation of optimal ratios of unit speeds vs. their number which fit in one chip. The results are compared with other known hardware platforms and illustrate progress in the cipher cracking systems which was made possible by improvements in the new FPGA technologies.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
Biham, E., Shamir, A.: Differential cryptanalysis of DES-like cryptosystems. J. Cryptol. 4(1), 3–72 (1991)
Curtin, M., Dolske, J.: A brute force search of DES keyspace. In: 8th Usenix Symposium, pp. 26–29 (1998)
distributed.net: Overview of the DES contests. https://www.distributed.net/DES. Accessed Mar 2019
Electronic Frontier Foundation: Cracking DES. Secrets of Encryption Research, Wiretap Politics, and Chip Design. O’Reilly Media (1998)
Guneysu, T., Paar, C., Pfeiffer, G., Schimmler, M.: Enhancing COPACOBANA for advanced applications in cryptography and cryptanalysis. In: 2008 International Conference on Field Programmable Logic and Applications, pp. 675–678. IEEE (2008)
Kumar, S., Paar, C., Pelzl, J., Pfeiffer, G., Schimmler, M.: Breaking ciphers with COPACOBANA – a cost-optimized parallel code breaker. In: Goubin, L., Matsui, M. (eds.) Cryptographic Hardware and Embedded Systems - CHES 2006. Lecture Notes in Computer Science, vol. 4249. Springer, Berlin, Heidelberg (2006)
Mazur, F.: FPGA hardware implementation of a cipher algorithm for cryptanalysis. Dissertation for BSc degree. Wrocław University of Science and Technology (2018). (in Polish)
National Institute of Standards and Technology: FIPS PUB 46-3 Data Encryption Standard (DES) (1999)
SciEngines Hardware. https://www.sciengines.com/technology-platform/sciengines-hardware. Accessed Mar 2019
Sugier, J.: Spartan FPGA devices in implementations of AES, BLAKE and KECCAK cryptographic functions. In: Zamojski, W., Mazurkiewicz, J., Sugier, J., Walkowiak, T., Kacprzyk, J. (eds.) Contemporary Complex Systems and Their Dependability, Proceedings of the Thirteenth International Conference on Dependability and Complex Systems DepCoS-RELCOMEX. AISC, vol. 761, pp. 461–470 (2019)
Xilinx, Inc.: 7 Series FPGAs Configurable Logic Block. UG474.PDF. www.xilinx.com. Accessed Mar 2019
Xilinx, Inc.: 7 Series FPGAs Data Sheet: Overview. DS180.PDF. www.xilinx.com. Accessed Mar 2019
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2020 Springer Nature Switzerland AG
About this paper
Cite this paper
Sugier, J. (2020). Cracking the DES Cipher with Cost-Optimized FPGA Devices. In: Zamojski, W., Mazurkiewicz, J., Sugier, J., Walkowiak, T., Kacprzyk, J. (eds) Engineering in Dependability of Computer Systems and Networks. DepCoS-RELCOMEX 2019. Advances in Intelligent Systems and Computing, vol 987. Springer, Cham. https://doi.org/10.1007/978-3-030-19501-4_47
Download citation
DOI: https://doi.org/10.1007/978-3-030-19501-4_47
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-19500-7
Online ISBN: 978-3-030-19501-4
eBook Packages: Intelligent Technologies and RoboticsIntelligent Technologies and Robotics (R0)