Abstract
An accumulator instruction set architecture is simpler than an instruction set of a (reduced instruction set computer) RISC architecture. Therefore, an accumulator instruction set that does within one instruction less than a typical RISC instruction is probably more “reduced” than a standard load/store register based RISC architecture.
This paper presents Leros, an accumulator machine and its supporting C compiler. The hypothesis of the Leros instruction set architecture is that it can deliver the same performance as a RISC pipeline, but consumes less hardware and therefore also less power.
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Notes
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The initial version of the processor has been designed on the island Leros: https://www.leros.gr/en/.
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- 4.
No accumulator optimizations
- 5.
No constant registers
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Schoeberl, M., Petersen, M.B. (2019). Leros: The Return of the Accumulator Machine. In: Schoeberl, M., Hochberger, C., Uhrig, S., Brehm, J., Pionteck, T. (eds) Architecture of Computing Systems – ARCS 2019. ARCS 2019. Lecture Notes in Computer Science(), vol 11479. Springer, Cham. https://doi.org/10.1007/978-3-030-18656-2_9
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