Abstract
This chapter covers a unique use of monolithic 3D technologies to improve FPGA design. It presents an FPGA architecture with logic programmable level plus independent routing programmable level. This leads to a futuristic FPGA in which structure and process similar to that of 3D NAND provide FPGA with lower cost and higher density than 2D Standard Cell design.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
N. Zhang, B. Brodersen, The cost of flexibility in systems on a chip design for signal processing applications. University of California, Berkeley, Tech. Rep. (2002)
B. Brodersen, Plenary Session, IEEE S3S 2013
M. Horowitz, 1.1 computing’s energy problem (and what we can do about it), in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (IEEE, 2014)
F.-L. Yuan et al., A multi-granularity FPGA with hierarchical interconnects for efficient and flexible mobile computing. IEEE J. Solid-State Circuits 50(1), 137–149 (2014)
T. Naito et al., World’s first monolithic 3D-FPGA with TFT SRAM over 90 nm 9-layer Cu CMOS, in 2010 Symposium on VLSI Technology (IEEE, 2010)
Y.Y. Liauw et al., Nonvolatile 3D-FPGA with monolithically stacked RRAM-based configuration memory, in 2012 IEEE International Solid-State Circuits Conference (IEEE, 2012)
A. Mihal, S. Teig, A constraint satisfaction approach for programmable logic detailed placement, in International Conference on Theory and Applications of Satisfiability Testing (Springer, Berlin, Heidelberg, 2013)
US Patent 8,912,820
O. Turkyilmaz et al., 3D FPGA using high-density interconnect Monolithic Integration, in 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) (IEEE, 2014)
US Patents: 6,642,744, 6,476,493, 6,819,136
Patent Application WO/2017/053329
Patent Application WO/2018/144957
C. Hu, Interconnect devices for field programmable gate array, in 1992 International Technical Digest on Electron Devices Meeting (IEEE, 1992)
US Patent 5,633,518
T. Speers et al., 0.25 µm FLASH memory based FPGA for space applications. System 10000, 100000 (1999): 1000000
D. Somasekhar, K. Roy, Differential current switch logic: a low power DCVS logic family. IEEE J. Solid-State Circuits 31(7), 981–991 (1996)
Liming Xiu, Time Moore: exploiting Moore’s law from the perspective of time. IEEE Solid-State Circuits Mag. 11, 39–55 (2019)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2020 Springer Nature Switzerland AG
About this chapter
Cite this chapter
Or-Bach, Z. (2020). 3D for Efficient FPGA. In: Murmann, B., Hoefflinger, B. (eds) NANO-CHIPS 2030. The Frontiers Collection. Springer, Cham. https://doi.org/10.1007/978-3-030-18338-7_11
Download citation
DOI: https://doi.org/10.1007/978-3-030-18338-7_11
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-18337-0
Online ISBN: 978-3-030-18338-7
eBook Packages: Physics and AstronomyPhysics and Astronomy (R0)