Abstract
Microelectronics architecture and packages are becoming complex with more number of components, including 3D stacks, getting integrated into a single package, called multi-chip packages (MCPs). MCPs are being used very widely in the microelectronics industry and enable increasing
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References
Ang Boon Chong, “Multi Chip Packaging (MCP) or Not MCP?”, Proc of the International MultiConference of Engineers and Computer Scientists (IMECS), vol. II, Mar. 2012
Alam, S.M., Jones, R.E., Pozder, S., Chatterjee, R., Jain, A., ‘Interstratum connection design considerations for cost-effective 3-D system integration’, IEEE Trans VLSI Systems, 18(3), pp. 450-460, 2010. (DOI: 10.1109/TVLSI.2008.2011910).
Banerjee, K., Souri, S.J., and Saraswat, K. C., ‘3-D ICs: A novel chip design for improving deep submicron interconnect performance and systems-on-chip integration’, Proc. IEEE, 89(5), pp. 602-633, 2001.
Brunschwiler T., Michel B., Rothuizen H., Kloter U., Wunderle B., Oppermann H. and Reichl H., “Interlayer Cooling Potential in Vertically Integrated Packages,” Microsystem Technol., 15(1), pp. 57-74, 2009.
Choobineh, L., Jain, A., ‘Analytical solution for steady-state and transient temperature field in vertically integrated three-dimensional integrated circuits (3D ICs)’, IEEE Trans Components, Packaging & Manufacturing Technologies, 2(12), pp. 2031-2039, 2012. (DOI: 10.1109/TCPMT.2012.2213820).
Choobineh, L., Jain, A., ‘Determination of temperature distribution in three-dimensional integrated circuits (3D ICs) with unequally-sized die’, Applied Thermal Engineering, 56, pp. 176-184, 2013. (DOI: 10.1016/j.applthermaleng.2013.03.006).
Choobineh, L., Agonafer, D., Jain, A., ‘Analytical modeling of temperature distribution in interposer-based microelectronic systems’, Proc. ASME/IEEE InterPACK 2013, San Francisco.
Chu, R.C., Simons, R.E., Ellsworth, M.J., Schmidt, R. R., Cozzolino, V., 2004, “Review of cooling technologies for computer products,” Device and Materials Reliability, IEEE Transactions, Vol. 4, Issue 4, pp. 568 – 585.
Cong, J., Luo, G., Wei, J. and Zhang, Y.: ‘Thermal-aware 3D IC placement via transformation’, Proc. Asia & South Pacific Design Automation Conf., pp. 780-785, 2007.
Dang, B., Bakir, M.S. ; Sekar, D.C. ; King, C.R. ; Meindl, J.D., ‘Integrated Microfluidic Cooling and Interconnects for 2D and 3D Chips,’ IEEE Trans. Adv. Packaging, 33, 2010, pp. 79-87.
Goplen, B. and Sapatnekar, S. S., ‘Placement of thermal vias in 3D ICs using various thermal objectives,’ IEEE Trans. Comput.-Aided Design of Integr. Circuits Syst., 26(4), pp. 692–709, 2006.
Huang W., Stan M. R., Skadron K., Sankaranarayanan K., Ghosh S., and Velusamy S., “Compact Thermal Modeling for Temperature-Aware Design.” In Proceedings of the 41st Design Automation Conference, June 2004.
Joshi, Y., ‘Reduced Order Thermal Models of Multiscale Microsystems,’ J. Heat Transfer, 134(3), 2012, 031008.
Jain, A., Alam, S.M., Pozder, S., Jones, R.E., ‘Thermal–electrical co-optimisation of floorplanning of three-dimensional integrated circuits under manufacturing and physical design constraints’, IET Computers & Digital Techniques (Special Issue on Three-dimensional Integrated Circuits Design), 5(3), pp. 169-178, 2011. (DOI: 10.1049/iet-cdt.2009.0107).
Kim Y.J., Joshi Y.K., Federov AG., Lee Y.J., Lim S.K., “Thermal Characterization of Interlayer Microfluidic Cooling of Three-Dimensional Integrated Circuits with Nonuniform Heat Flux,” ASME J. Heat Transfer, 132, 041009-1, 2010.
Loh, G., Xie, Y., and Black, B.: ‘Processor design in three-dimensional die-stacking technologies’, IEEE Micro, 27(3), pp. 31-48, 2007.
Mahajan, R., Chiu, C. P., & Chrysler, G. (2006). “Cooling a microprocessor chip.” Proceedings of the IEEE, 94(8), 1476-1486.
Matthew, R., Manickaraj, K., Sullivan, O., Mukhopadhyay, S. and Kumar, S., “Hotspot Cooling in Stacked Chips using Thermoelectric Coolers,” IEEE Transactions on Components and Packaging Technologies, 3 (5), 759-767, 2013.
Patti, R.: ‘Three-dimensional integrated circuits and the future of system-on-chip designs’, Proc. IEEE, 94(6), pp. 1214-1224, 2006.
Polka, L. A., Kalyanam, H., Hu, G., Krishnamoorthy S., “Package Technology to address the memory bandwidth challenge for Tera-scale computing”, Intel Technology Journal, vol. 11, issue 03, August 2007.
Shaukatullah, H., 1999, “Bibliography of liquid cooled heat sinks for thermal enhancement of electronic packages,” Semiconductor Thermal Measurement and Management Symposium.
Sauciuc, I., Prasher, R., Chang, J. Y., Erturk, H., Chrysler, G., Chiu, C. P., Mahajan, R., “Thermal performance and key challenges for future CPU cooling technologies.” Proceedings of IPACK 2005, ASME InterPACK ’05, July 17-22, Sanfrancisco, California, USA.
Venkatadri, V., Sammakia, B., Srihari, K., Santos, D., ‘A review of recent advances in thermal management in three dimensional chip stacks in electronic systems’, ASME J. Electronic Packaging, 133, pp. 041011-1, 2011.
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Jha, C.M., Choobineh, L., Jain, A. (2015). Microelectronics Thermal Sensing: Future Trends. In: Jha, C. (eds) Thermal Sensors. Springer, New York, NY. https://doi.org/10.1007/978-1-4939-2581-0_5
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