Abstract
In this chapter, we present a system-level framework for designing minimal deterministic routing algorithms for Networks-on-Chip (NoCs) that are customized for a set of applications. To this end, we first formulate an optimization problem of minimizing average packet latency in the network and then use the simulated annealing heuristic to solve this problem. To estimate the average packet latency we use a queueing-based analytical model which can capture the burstiness of the traffic. The proposed framework does not require virtual channels to guarantee deadlock freedom since routes are extracted from an acyclic channel dependency graph. Experiments with both synthetic and realistic workloads show the effectiveness of the approach. Results show that maximum sustainable throughput of the network is improved for different applications and architectures.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
K. Bondalapati, V.K. Prasanna, Reconfigurable computing systems. Proc. IEEE 90(7), 1201–1217 (2002)
O. Catoni, Metropolis, simulated annealing, and iterated energy transformation algorithms, theory and experiments. J. Complex. 12(4), 595–623 (1996)
V. Cerny, Thermodynamical approach to the traveling salesman problem: An efficient simulation algorithm. J. Opt. Theory. Appl. 45, 41–45 (1985)
G.-M. Chiu, The odd-even turn model for adaptive routing. IEEE Trans. Parall. Distr. Syst. 11(7), 729–738 (2000)
W.J. Dally, B. Towles, Principles and practices of interconnection networks, 1st edn. (Morgan Kaufmann, San Francisco, 2004)
W.J. Dally, C.L. Seitz, Deadlock-free message routing in multiprocessor interconnection networks. IEEE Trans. Comput. 36(5), 547–553 (1987)
J. Duato, C. Yalamanchili, L. Ni, Interconnection Networks: An Engineering Approach (IEEE Computer Society Press, Los Alamitos, Morgan Kaufmann, San Francisco, 2003)
W. Fischer, K. Meier-Hellstern, The Markov-Modulated Poisson Process (MMPP) cookbook. Perform. Evaluat. 18(2), 149–171 (1993)
C.J. Glass, L.M. Ni, The turn model for adaptive routing. J. Assoc. Comput. Mach. 41(5), 874–902 (1994)
P. Guerrier, A. Greiner, A generic architecture for on-chip packet-switched interconnections, in Proceedings of the Design, Automation, and Test in Europe (Paris, France, 2000), pp. 250–256
A. Hemani et~al., Network on a chip: An architecture for billion transistor era, in Proceedings of the IEEE NorChip (Turku, Finland, 2000), pp. 166–173
J. Hu, R. Marculescu, DyAD – smart routing for networks-on-chip, in Proceedings of the Design Automation Conference (San Diego, 2004), pp. 260–263
J. Hu, R. Marculescu, Energy- and performance-aware mapping for regular NoC architectures. IEEE Trans. Comp. Aid. Des. Integr. Circuit. Syst. 24(4), 551–562 (2005)
A.E. Kiasari, Z. Lu, A. Jantsch, An analytical latency model for networks-on-chip. IEEE Trans. VLSI Syst. 21(1), 113–123 (2013)
A.E. Kiasari, A. Jantsch, Z. Lu, A framework for designing congestion-aware deterministic routing, in Proceedings of the 3rd International Workshop on Network-on-Chip Architectures (NoCArc), Held in conjunction with the 43rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-43) (Atlanta, 2010), pp. 45–50
M.A. Kinsy et~al., Application-aware deadlock-free oblivious routing, in Proceedings of the ISCA (Austin, 2009), pp. 208–219
S. Kirkpatrick, C.D. Gelatt, M.P. Vecchi, Optimization by simulated annealing. Science 220(4598), 671–680 (1983)
S. Murali et al., Analysis of error recovery schemes for networks on chips. IEEE Des. Test Comp. 22(5), 434–442 (2005)
M. Palesi et al., Application specific routing algorithms for networks on chip. IEEE Trans. Parall. Distr. Syst. 20(3), 316–330 (2009)
K. Pawlikowski, Steady-state simulation of queueing processes: A survey of problems and solutions. ACM Comput. Surv. 22(2), 123–170 (1990)
C. Sechen, A. Sangiovanni-Vincentelli, The TimberWolf placement and routing package. J. Sol. State Circuit. SC-20, 510–522 (1985)
V. Soteriou, H. Wang, L.-S. Peh, A statistical traffic model for on-chip interconnection networks, in Proceedings of the MASCOTS (Monterey, 2006), pp. 104–116
W. Trumler et al., Self-optimized routing in a network-on-a-chip. IFIP World Comp. Cong. 268, 199–212 (2008)
E.B. van der Tol, E.G. Jaspers, Mapping of MPEG-4 decoding on a flexible architecture platform. SPIE 4674, 1–13 (2002)
G. Varatkar, R. Marculescu, Traffic analysis for on-chip networks design of multimedia applications, in Proceedings of the Design Automation Conference (New Orleans, 2002), pp. 795–800
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2014 Springer Science+Business Media New York
About this chapter
Cite this chapter
Kiasari, A.E., Jantsch, A., Lu, Z. (2014). A Heuristic Framework for Designing and Exploring Deterministic Routing Algorithm for NoCs. In: Palesi, M., Daneshtalab, M. (eds) Routing Algorithms in Networks-on-Chip. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-8274-1_2
Download citation
DOI: https://doi.org/10.1007/978-1-4614-8274-1_2
Published:
Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4614-8273-4
Online ISBN: 978-1-4614-8274-1
eBook Packages: EngineeringEngineering (R0)