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A Study on Improving Polishing Process Effectiveness for Silicon Reclaim Wafer

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Intelligent Technologies and Engineering Systems

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 234))

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Abstract

In this study we improve the capacity of the polishing process of silicon reclaim wafer by applying the six sigma approach and the five steps of DMAIC. Based on the Taguchi experiment approach, a four-factor three-level experiment is designed by experimental design method using the existing polishing parameters, in particular such processing conditions as the cylinder head down force of the main process section, the PP rpm, LP rpm, and the flow of polishing slurry. The four factors are as follows: cylinder head down force, PP rpm, LP rpm, and the slurry flow. By studying the correlation between various parameters in the polishing process and the polishing result, the polishing factors’ effect on the material removal rate (MRR) and wafer’s total thickness variation (TTV) after the polishing process is analyzed, to obtain the optimized parameters for the improvement of the quality of polishing process and enhancement of process yield rate.

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Chang, CP., Wang, WL., Kuo, YC. (2013). A Study on Improving Polishing Process Effectiveness for Silicon Reclaim Wafer. In: Juang, J., Huang, YC. (eds) Intelligent Technologies and Engineering Systems. Lecture Notes in Electrical Engineering, vol 234. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-6747-2_96

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  • DOI: https://doi.org/10.1007/978-1-4614-6747-2_96

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  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4614-6746-5

  • Online ISBN: 978-1-4614-6747-2

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