Abstract
Applications of arithmetic operations in integrated circuits are manifold. In most of the digital systems, adders are the fundamental component in the design of application specific integrated circuits like RISC processors, Digital Signal Processors (DSP), microprocessors etc. This paper focuses two main design approaches. The former presents the problems identified in the existing Gate Diffusion Input (GDI) technique and its design solution in Modified Gate Diffusion Input (MGDI). The primitive logic cells are construction in MGDI and its performance issues are compared with existing GDI. The latter presents the implementation of 3 different MGDI full adders and a complete verification and comparison is also carried out to test the performance of the proposed adders. The performance analysis has been evaluated by Tanner simulator using TSMC 0.250 \(\upmu \)m technologies. The simulation results reveal better delay and power performance of proposed adder cells as compared to GDI, PT and CMOS at 0.250 \(\upmu \)m technologies.
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Uma, R., Dhavachelvan, P. (2013). Low Power and High Speed Adders in Modified Gated Diffusion Input Technique. In: Chaki, N., Meghanathan, N., Nagamalai, D. (eds) Computer Networks & Communications (NetCom). Lecture Notes in Electrical Engineering, vol 131. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-6154-8_24
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DOI: https://doi.org/10.1007/978-1-4614-6154-8_24
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