Abstract
The paper presents a novel method for teaching courses about logical circuits. Attracting students’ interest is an issue that is being addressed in all courses. In general, students are more interested in doing practical exercises then learning theory and calculating or designing things on a piece of paper. In courses devoted to logic circuits design it is especially important that the students have the possibility to verify their designs and to experiment with various variations. Using universal virtual verification panel, the lessons can be more understandable. Our solution has limitation for logical gates as formerly had physical verification panels but also many other features which can be used during education. Experimental results show, that 90.2 % of students think that our solution is better than the old one [1].
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References
LOG (2009) The chipmunk logic simulator (User’s guide). Avaiable at http://caltechcstr.library.caltech.edu/377/. Accessed 11 Nov 2009
LogiSim (2009). Available at http://www.tetzl.de/logicsim_applet.html. Accessed 10 Nov 2009
Multisim (2009). Available at http://www.ni.com/multisim/. Accessed 10 Oct 2009
Simcir (2009). Available at http://www.d-project.com/simcir/simcir.htm. Accessed 10 Oct 2009
Logicly (2009). Available at http://joshblog.net/projects/logic-gate-simulator/Logicly.html. Accessed 15 Nov 2009
HTP: Universal virtual verification panel of logic circuits. Available at http://www2.dcs.fiit.stuba.sk/TeamProject/2009/team06pss/
Bača J, Giertl J (2004) Decomposition of logical systems described by algebraic expressions. In: Proceedings of the sixth international scientific conference electronic computers and informatics ECI 2004, Košice-Herľany, Slovakia, Košice, VIENALA Press, Košice, 22–24. Sep. 2004, pp 111–116
Jelemenská K, Čičák P, Jurikovič M, Pištek P (2010) Digital system description knowledge assessment. In: Elleithy K, Sobh T, Iskander M, Kapila V, Karim MA, Mahmood A (eds) Technological developments in networking, education and automation. International joint conferences on computer, information, and systems sciences, and engineering (CISSE 09), vol 1, Bridgeport, Connecticut, USA, Springer, Dordrecht, Dec 4–12 2009, pp 127–132
Jurikovič M, Jelemenská K, Čičák P (2010) Parallel controller design and synthesis. In: 7th FPGAworld conference, Academic Proceedings 2010, Copenhagen, Denmark, Sep 6 2010, pp 35–41
Bača J (1977) Logical circuits (in Slovak). Alfa, Bratislava
Frištacký N, Kolenička J, Kolesár M (1986) Logic systems—combinational circuits (in Slovak). SVŠT, Bratislava
Hlavatý J, Kolesár M (1973) Logic circuits—combinational networks—examples (in Slovak). SVŠT, Bratislava
Ambler SW (2010) User interface design tips, techniques, and principles. Available at http://www.ambysoft.com/essays/userInterfaceDesign.html. Accessed 15 Feb 2010
IEEE: IEEE standard graphic symbols for logic functions (ANSI/IEEE Std 91a-1991) (2010). Available at http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=27895&isnumber=11. Accessed 15 Feb 2010
Oracle (2010) Introduction to DnD. Available at http://java.sun.com/docs/books/tutorial/uiswing/dnd/intro.html. Accessed 15 Feb 2010
Oracle (2010) Implementing serializable. Available at http://www.javapractices.com/topic/TopicAction.do?Id=45. Accessed 15 Feb 2010
Oracle (2010) Interface serializable. Available at http://java.sun.com/j2se/1.4.2/docs/api/java/io/Serializable.html. Accessed 15 Feb 2010
Oracle (2010) Socket communications. Available at http://java.sun.com/developer/onlineTraining/Programming/BasicJava2/socket.html. Accessed 15 Feb 2010
Rayson S, Aberdour M (2010) Virtual classrooms: an overview. Available at http://www.kineoopensource.com/downloads/kos_reports/Virtual_Classrooms_Overview_v1.0.pdf. Accessed 15 Feb 2010
Acknowledgments
This work was supported by Slovak Science Grant Agency (VEGA VG 1/0649/09 “Security and Reliability in Distributed Systems and Mobile Networks”).
The authors thank Elena Tomalova for her help during testing HTP on students.
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Pištek, P., Marcinčin, R., Palaj, T., Štrba, J. (2013). Logical Circuits Design Education Based on Virtual Verification Panel. In: Sobh, T., Elleithy, K. (eds) Emerging Trends in Computing, Informatics, Systems Sciences, and Engineering. Lecture Notes in Electrical Engineering, vol 151. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-3558-7_77
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