Abstract
The term “Synopsys Design Constraints” (aka SDC) is used to describe design requirements for timing, power, and area and is the most commonly used format by EDA tools used for synthesis, static timing analysis, and place and route. This chapter provides a brief history of timing constraints and an overview of the SDC language.
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© 2013 Springer Science+Business Media New York
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Gangadharan, S., Churiwala, S. (2013). SDC Extensions Through Tcl. In: Constraining Designs for Synthesis and Timing Analysis. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-3269-2_4
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DOI: https://doi.org/10.1007/978-1-4614-3269-2_4
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Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4614-3268-5
Online ISBN: 978-1-4614-3269-2
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