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Reconfigurable Intercommunication Infrastructure: NoCs

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Adaptable Embedded Systems

Abstract

Network-on-Chip, usually referred as NoC, has replaced the common bus due to its scalability and reliability in the multi and many core scenarios. Therefore, in this chapter, we discuss how a NoC may adapt to provide the best response to the different requirements of nowadays heterogeneous applications running on complex System-on-Chips. We discuss adaptability in the NoC by considering three different levels: protocol, architecture and link levels. For each of them, there are specific adaptive techniques that have been proposed to improve performance, reliability, yield and/or reduce power and energy consumption.

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References

  1. Al Faruque, M.A., Ebi, T., Henkel, J.: Roadnoc: runtime observability for an adaptive network on chip architecture. In: Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, ICCAD ’08, pp. 543–548. IEEE, Piscataway (2008). http://dl.acm.org/citation.cfm?id=1509456.1509577

  2. Al Faruque, M.A., Ebi, T., Henkel, J.: Configurable links for runtime adaptive on-chip communication. In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE ’09, pp. 256–261. European Design and Automation Association 3001, Leuven (2009). http://dl.acm.org/citation.cfm?id=1874620.1874680

  3. Bartic, T.A., Mignolet, J.Y., Nollet, V., Marescaux, T., Verkest, D., Vernalde, S., Lauwereins, R.: Topology adaptive network-on-chip design and implementation. IEE Proc. Comput. Digit. Tech. 152(4), 467 (2005). http://www.uoguelph.ca/~jernst/documents/topologyadaptivenocd%esignandimp.pdf

    Google Scholar 

  4. Beigne, E., Vivet, P.: Design of on-chip and off-chip interfaces for a gals noc architecture. In: Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC ’06, pp. 172–. IEEE Computer Society, Washington, DC (2006). doi:10.1109/ASYNC.2006.16. http://dx.doi.org/10.1109/ASYNC.2006.16

  5. Benini, L., De Micheli, G.: Networks on chips: a new soc paradigm. Computer 35(1), 70–78 (2002). doi:10.1109/2.976921. http://dx.doi.org/10.1109/2.976921

    Google Scholar 

  6. Bertozzi, D., Jalabert, A., Murali, S., Tamhankar, R., Stergiou, S., Benini, L., De Micheli, G.: Noc synthesis flow for customized domain specific multiprocessor systems-on-chip. IEEE Trans. Parallel Distrib. Syst. 16(2), 113–129 (2005). doi:10.1109/TPDS.2005.22. http://dx.doi.org/10.1109/TPDS.2005.22

  7. Bertozzi, S., Acquaviva, A., Bertozzi, D., Poggiali, A.: Supporting task migration in multi-processor systems-on-chip: a feasibility study. In: Proceedings of the Conference on Design, Automation and Test in Europe: Proceedings, DATE ’06, pp. 15–20. European Design and Automation Association 3001, Leuven (2006). http://portal.acm.org/citation.cfm?id=1131481.1131488

  8. Bjerregaard, T., Mahadevan, S.: A survey of research and practices of network-on-chip. ACM Comput. Surv. 38 (2006). doi:http://doi.acm.org/http://doi.acm.org/10.1145/1132952.1132953

  9. Bourduas, S., Zilic, Z.: A hybrid ring/mesh interconnect for network-on-chip using hierarchical rings for global routing. In: Proceedings of the First International Symposium on Networks-on-Chip, NOCS ’07, pp. 195–204. IEEE Computer Society, Washington, DC (2007). doi:http://dx.doi.org/10.1109/NOCS.2007.3

  10. Brião, E.W., Barcelos, D., Wagner, F.R.: Dynamic task allocation strategies in mpsoc for soft real-time applications. In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE ’08, pp. 1386–1389. ACM, New York (2008). doi:10.1145/1403375.1403709. http://doi.acm.org/10.1145/1403375.1403709

  11. Chan, J., Parameswaran, S.: Nocout: Noc topology generation with mixed packet-switched and point-to-point networks. In: Proceedings of the 2008 Asia and South Pacific Design Automation Conference, ASP-DAC ’08, pp. 265–270. IEEE Computer Society, Los Alamitos (2008). http://portal.acm.org/citation.cfm?id=1356802.1356869

  12. Chen, X., Peh, L.S.: Leakage power modeling and optimization in interconnection networks. In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, ISLPED ’03, pp. 90–95. ACM, New York (2003). DOI 10.1145/871506.871531. URL http://doi.acm.org/10.1145/871506.871531

  13. Chou, S.H., Chen, C.C., Wen, C.N., Chen, T.F., Lin, T.J.: Hierarchical circuit-switched noc for multicore video processing. Microprocess. Microsyst. 35(2), 182–199 (2011). doi:10.1016/j.micpro.2010.09.009. http://dx.doi.org/10.1016/j.micpro.2010.09.009

    Google Scholar 

  14. Concatto, C., Kologeski, A., Carro, L., Kastensmidt, F.L., Palermo, G., Silvano, C.: Two-levels of adaptive buffer for virtual channel router in nocs. In: VLSI-SoC, pp. 302–307. IEEE, Hong Kong (2011)

    Google Scholar 

  15. Dally, W.J., Towles, B.: Route packets, not wires: on-chip inteconnection networks. In: DAC ’01: Proceedings of the 38th Conference on Design Automation, pp. 684–689. ACM, New York (2001). doi:http://doi.acm.org/10.1145/378239.379048

  16. De Micheli, G., Seiculescu, C., Murali, S., Benini, L., Angiolini, F., Pullini, A.: Networks on chips: From research to products. In: Design Automation Conference (DAC), 2010 47th ACM/IEEE, pp. 300–305. IEEE, Piscataway (2010)

    Google Scholar 

  17. de Paulo, V., Ababei, C.: 3d network-on-chip architectures using homogeneous meshes and heterogeneous floorplans. Int. J. Reconfig. Comput. 2010, 1:1–1:12 (2010). doi:10.1155/2010/603059. http://dx.doi.org/10.1155/2010/603059

    Google Scholar 

  18. Duato, J., Yalamanchili, S., Ni, L.: Interconnection Networks: An Engineering Approach, 1st edn. IEEE Computer Society, Los Alamitos (1997)

    Google Scholar 

  19. Edwards, D., Nunez-Yanez, J.Y., Coppola, A.: Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems. In: IET Computers & Digital Technique, pp. 184–198 (2008). doi:10.1049/iet-cdt:20060175

    Google Scholar 

  20. Gilabert, F., Ludovici, D., Medardoni, S., Bertozzi, D., Benini, L., Gaydadjiev, G.: Designing regular network-on-chip topologies under technology, architecture and software constraints. nternational conference on complex, intelligent and software intensive systems, vol. 0, pp. 681–687 (2009). doi:http://doi.ieeecomputersociety.org/10.1109/CISIS.2009.30

  21. Held, J., Koehl, S.: Introducing the singlechip cloud computer exploring the future of many-core processors pp. 1–5 (2010). http://newsroom.intel.com/servlet/JiveServlet/previewBody/1088-102-1-1165/Intel_SCC_whitepaper_4302010.pdf

  22. Hu, J., Marculescu, R.: Energy- and performance-aware mapping for regular noc architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4), 551–562 (2005)

    Article  Google Scholar 

  23. Hu, J., Ogras, U.Y., Marculescu, R.: System-level buffer allocation for application-specific networks-on-chip router design. Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12), 2919–2933 (2006). doi:10.1109/TCAD.2006.882474. http://dx.doi.org/10.1109/TCAD.2006.882474

  24. ITRS: System drivers (2010). http://www.itrs.net/Links/2010ITRS/Home2010.htm

  25. Jerraya, A., Tenhunen, H., Wolf, W.: Guest editors’ introduction: Multiprocessor systems-on-chips. Computer 38(7), 36–40 (2005). doi:10.1109/MC.2005.231

    Article  Google Scholar 

  26. Koibuchi, M., Matsutani, H., Amano, H., Pinkston, T.M.: A lightweight fault-tolerant mechanism for network-on-chip. In: Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip, NOCS ’08, pp. 13–22. IEEE Computer Society, Washington, DC (2008). http://portal.acm.org/citation.cfm?id=1397757.1397982

  27. Kologeski, A., Concatto, C., Carro, L., Kastensmidt, F.: Improving reliability in nocs by application-specific mapping combined with adaptive fault-tolerant method in the links. In: European Test Symposium (ETS), 2011 16th IEEE, pp. 123–128 (2011). doi:10.1109/ETS.2011.62

    Google Scholar 

  28. Kologeski, A., Concatto, C., Kastensmidt, F., Carro, L.: Adnoc case-study for mpeg4 benchmark: improving performance and saving energy with an adaptive noc. In: Proceedings of the 24th symposium on Integrated circuits and systems design, SBCCI ’11, pp. 209–214. ACM, New York (2011). doi:http://doi.acm.org/10.1145/2020876.2020924

  29. Kreutz, M.E., Marcon, C.A.M., Carro, L., Susin, A.A., Calazans, N.L.V.: Energy and latency evaluation of noc topologies. In: ISCAS (6), pp. 5866–5869. IEEE Kobe, Japan (2005)

    Google Scholar 

  30. Kumar, A., Peh, L.S., Kundu, P., Jha, N.: Toward ideal on-chip communication using express virtual channels. Micro IEEE 28(1), 80–90 (2008). doi:10.1109/MM.2008.18

    Article  Google Scholar 

  31. Lai, G., Lin, X.: Floorplan-aware application-specific network-on-chip topology synthesis using genetic algorithm technique. J. Supercomput. 1–20 (2011). doi:10.1007/s11227-011-0599-z. http://dx.doi.org/10.1007/s11227-011-0599-z

  32. Lan, Y.C., Lin, H.A., Lo, S.H., Hu, Y.H., Chen, S.J.: A bidirectional noc (binoc) architecture with dynamic self-reconfigurable channel. Trans. Comput. Aided Des. Integr. Circuits Syst 30(3), 427–440 (2011). doi:10.1109/TCAD.2010.2086930. http://dx.doi.org/10.1109/TCAD.2010.2086930

    Google Scholar 

  33. Lankes, A., Herkersdorf, A., Sonntag, S., Reinig, H.: Noc topology exploration for mobile multimedia applications. In: ICECS, pp. 707–710. IEEE Yasmine Hammamet, Tunesia (2009)

    Google Scholar 

  34. Li, X., Cao, Y., Wang, L., Cai, T.: Fault-tolerant routing algorithm for network-on-chip based on dynamic xy routing. Wuhan. Univ. J. Natural Sci. 14, 343–348 (2009). doi:10.1007/s11859-009-0412-5. http://dx.doi.org/10.1007/s11859-009-0412-5

  35. Majeti, D., Pasalapudi, A., Yalamanchili, K.: Low energy tree based network on chip architectures using homogeneous routers for bandwidth and latency constrained multimedia applications. International conference on emerging trends in engineering & technology, vol. 0, pp. 358–363 (2009). doi:http://doi.ieeecomputersociety.org/10.1109/ICETET.2009.139

  36. Manferdelli, J.L., Govindaraju, N.K., Crall, C.: Challenges and opportunities in many-core computing. Proc. IEEE 96(5), 808–815 (2008). http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=4484943

    Google Scholar 

  37. Marcon, C., Borin, A., Susin, A., Carro, L., Wagner, F.: Time and energy efficient mapping of embedded applications onto nocs. In: Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC ’05, pp. 33–38. ACM, New York (2005). doi:http://doi.acm.org/10.1145/1120725.1120738

  38. Matos, D., Concatto, C., Kologeski, A., Carro, L., Kreutz, M., Kastensmidt, F., Susin, A.: A noc closed-loop performance monitor and adapter. Microprocess. Microsyst. (0) (2011). doi:10.1016/j.micpro.2011.05.001. http://www.sciencedirect.com/science/article/pii/S0141933111000615

  39. Matos, D., Concatto, C., Kreutz, M., Kastensmidt, F., Carro, L., Susin, A.: Reconfigurable routers for low power and high performance. IEEE Trans. Very Large Scale Integr. Syst. 19(11), 2045–2057 (2011). doi:10.1109/TVLSI.2010.2068064

    Article  Google Scholar 

  40. Micheli, G.D., Benini, L.: On-Chip Communication Architectures: System on Chip Interconnect. Morgan Kaufmann, San Francisco (2008)

    Google Scholar 

  41. Miro Panades, I., Greiner, A.: Bi-synchronous fifo for synchronous circuit communication well suited for network-on-chip in gals architectures. In: Proceedings of the First International Symposium on Networks-on-Chip, NOCS ’07, pp. 83–94. IEEE Computer Society, Washington, DC (2007). doi:10.1109/NOCS.2007.14. http://dx.doi.org/10.1109/NOCS.2007.14

  42. Modarressi, M., Sarbazi-Azad, H., Arjomand, M.: A hybrid packet-circuit switched on-chip network based on sdm. In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE ’09, pp. 566–569. European Design and Automation Association 3001, Leuven (2009). http://dl.acm.org/citation.cfm?id=1874620.1874758

  43. Modarressi, M., Tavakkol, A., Sarbazi-Azad, H.: Application-aware topology reconfiguration for on-chip networks. IEEE Trans. Very Large Scale Integr. Syst. PP(99), 1–13 (2010). doi:10.1109/TVLSI.2010.2066586

    Google Scholar 

  44. Modarressi, M., Tavakkol, A., Sarbazi-Azad, H.: Virtual point-to-point connections for nocs. Trans. Comput. Aided Des. Integr. Circuits Syst 29(6), 855–868 (2010). doi:10.1109/TCAD.2010.2048402. http://dx.doi.org/10.1109/TCAD.2010.2048402

  45. Murali, S., De Micheli, G.: Sunmap: a tool for automatic topology selection and generation for nocs. In: Proceedings of the 41st Annual Design Automation Conference, DAC ’04, pp. 914–919. ACM, New York (2004). doi:http://doi.acm.org/10.1145/996566.996809. http://doi.acm.org/10.1145/996566.996809

  46. Jerger, N., Peh, L., Lipasti, M.: Circuit-switched coherence. In: NoCS, pp. 193–202 (2008)

    Google Scholar 

  47. Neishaburi, M.H., Zilic, Z.: Reliability aware noc router architecture using input channel buffer sharing. In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI, GLSVLSI ’09, pp. 511–516. ACM, New York (2009). doi:10.1145/1531542.1531658. http://doi.acm.org/10.1145/1531542.1531658

  48. Ngo, V.D., Nguyen, H.N., Choi, H.W.: Analyzing the performance of mesh and fat-tree topologies for network on chip design. In: L. Yang, M. Amamiya, Z. Liu, M. Guo, F. Rammig (eds.) Embedded and Ubiquitous Computing EUC 2005. Lecture Notes in Computer Science, vol. 3824, pp. 300–310. Springer, Berlin/Heidelberg (2005)

    Chapter  Google Scholar 

  49. Nicopoulos, C., Park, D., Kim, J., Vijaykrishnan, N., Yousif, M., Das, C.: Vichar: A dynamic virtual channel regulator for network-on-chip routers. In: 39th Annual IEEE/ACM International Symposium on Microarchitecture, 2006. MICRO-39, pp. 333–346 (2006). doi:10.1109/MICRO.2006.50

    Google Scholar 

  50. Nollet, V., Marescaux, T., Avasare, P., Verkest, D., Mignolet, J.Y.: Centralized run-time resource management in a network-on-chip containing reconfigurable hardware tiles. In: Proceedings of the Conference on Design, Automation and Test in Europe – Volume 1, DATE ’05, pp. 234–239. IEEE Computer Society, Washington, DC (2005). doi:http://dx.doi.org/10.1109/DATE.2005.91

  51. Owens, J.D., Dally, W.J., Ho, R., Jayasimha, D.N.J., Keckler, S.W., Peh, L.S.: Research challenges for on-chip interconnection networks. IEEE Micro 27, 96–108 (2007). doi:10.1109/MM.2007.91. http://portal.acm.org/citation.cfm?id=1320302.1320841

    Google Scholar 

  52. Palermo, G., Mariani, G., Silvano, C., Locatelli, R., Coppola, M.: Mapping and topology customization approaches for application-specific stnoc designs. In: ASAP, pp. 61–68. IEEE Computer Society Montreal, Canada (2007).

    Google Scholar 

  53. Park, D., Nicopoulos, C., Kim, J., Vijaykrishnan, N., Das, C.R.: Exploring fault-tolerant network-on-chip architectures. In: Proceedings of the International Conference on Dependable Systems and Networks, pp. 93–104. IEEE Computer Society, Washington, DC (2006). doi:10.1109/DSN.2006.35. http://portal.acm.org/citation.cfm?id=1135532.1135690

  54. Rantala, V., Lehtonen, T., Plosila, J.: Network on chip routing algorithms TUCS Technical Report 779. Turku Centre of Computer Science. pp. 1–34. (2006)

    Google Scholar 

  55. Schonwald, T., Zimmermann, J., Bringmann, O., Rosenstiel, W.: Fully adaptive fault-tolerant routing algorithm for network-on-chip architectures. In: Euromicro Symposium on Digital Systems Design, pp. 527–534 (2007). doi:10.1109/DSD.2007.4341518

    Google Scholar 

  56. Seiculescu, C., Murali, S., Benini, L., De Micheli, G.: Sunfloor 3d: a tool for networks on chip topology synthesis for 3-d systems on chips. Trans. Comput. Aided Des. Integr. Circuits Syst. 29(12), 1987–2000 (2010). doi:10.1109/TCAD.2010.2061610. http://dx.doi.org/10.1109/TCAD.2010.2061610

  57. Sheibanyrad, A., Greiner, A.: Hybrid-timing fifos to use on networks-on-chip in gals architectures. In: Arabnia, H.R., Yang, L.T. (eds.) ESA, pp. 27–33. Las Vegas, USA CSREA Press (2007)

    Google Scholar 

  58. Singh, A., Jigang, W., Prakash, A., Srikanthan, T.: Mapping algorithms for noc-based heterogeneous mpsoc platforms. In: 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, 2009. DSD ’09, pp. 133–140 (2009). doi:10.1109/DSD.2009.145

    Google Scholar 

  59. Srinivasan, K., Chatha, K.S.: A low complexity heuristic for design of custom network-on-chip architectures. In: Proceedings of the Conference on Design, Automation and Test in Europe: Proceedings, DATE ’06, pp. 130–135. European Design and Automation Association 3001, Leuven (2006). http://dl.acm.org/citation.cfm?id=1131481.1131521

  60. St, http://www.st.com/internet/mcu/family/169.jsp

  61. Stensgaard, M.B., Sparsø, J.: Renoc: A network-on-chip architecture with reconfigurable topology. In: Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip, NOCS ’08, pp. 55–64. IEEE Computer Society, Washington, DC (2008). http://dl.acm.org/citation.cfm?id=1397757.1397985

  62. Strano, A., Ludovici, D., Bertozzi, D.: A library of dual-clock fifos for cost-effective and flexible mpsoc design. In: 2010 International Conference on Embedded Computer Systems (SAMOS), pp. 20–27 (2010). doi:10.1109/ICSAMOS.2010.5642098

    Google Scholar 

  63. Tamir, Y., Frazier, G.L.: Dynamically-allocated multi-queue buffers for vlsi communication switches. IEEE Trans. Comput. 41(6), 725–737 (1992). doi:10.1109/12.144624. http://dx.doi.org/10.1109/12.144624

    Google Scholar 

  64. Texas, http://focus.ti.com/general/docs/gencontent.tsp?contentid=46946

  65. Thonnart, Y., Beigné, E., Vivet, P.: Design and implementation of a gals adapter for anoc based architectures. In: Proceedings of the 2009 15th IEEE Symposium on Asynchronous Circuits and Systems (async 2009), ASYNC ’09, pp. 13–22. IEEE Computer Society, Washington, DC (2009). doi:10.1109/ASYNC.2009.13. http://dx.doi.org/10.1109/ASYNC.2009.13

  66. Tilera, http://www.tilera.com/products/processors/tile64

  67. Véstias, M.P., Neto, H.C.: Area and performance optimization of a generic network-on-chip architecture. In: Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, SBCCI ’06, pp. 68–73. ACM, New York (2006). doi:http://doi.acm.org/10.1145/1150343.1150365

  68. Yan, S., Lin, B.: Design Automation Conference, 2008. ASPDAC 2008. Asia and South Pacific. In: Application-specific Network-on-Chip architecture synthesis based on set partitions and Steiner Trees, ’3, pp. 277–282 (2008) doi:10.1109/ASPDAC.2008. 4483955

    Google Scholar 

  69. Ye, T.T., Micheli, G.D., Benini, L.: Analysis of power consumption on switch fabrics in network routers. In: Proceedings of the 39th Annual Design Automation Conference, DAC ’02, pp. 524–529. ACM, New York (2002). doi:10.1145/513918.514051. http://doi.acm.org/10.1145/513918.514051

  70. Yoon, Y.J., Concer, N., Petracca, M., Carloni, L.: Virtual channels vs. multiple physical networks: a comparative analysis. In: Proceedings of the 47th Design Automation Conference, DAC ’10, pp. 162–165. ACM, New York (2010). doi:10.1145/1837274.1837315. http://doi.acm.org/10.1145/1837274.1837315

  71. Yu, B., Dong, S., Chen, S., Goto, S.: Floorplanning and topology generation for application-specific network-on-chip. In: Proceedings of the 2010 Asia and South Pacific Design Automation Conference, ASPDAC ’10, pp. 535–540. IEEE, Piscataway (2010). http://portal.acm.org/citation.cfm?id=1899721.1899847

  72. Zeferino, C.A., Kreutz, M.E., Susin, A.A.: Rasoc: A router soft-core for networks-on-chip. In: Proceedings of the Conference on Design, Automation and Test in Europe – Volume 3, DATE ’04, p. 198–203. IEEE Computer Society, Washington, DC, USA (2004). http://dl.acm.org/citation.cfm?id=968880.969275

  73. Zhu, H., Pande, P.P., Grecu, C.: Performance evaluation of adaptive routing algorithms for achieving fault tolerance in noc fabrics. In: ASAP, pp. 42–47. Montreal, Canada IEEE Computer Society (2007)

    Google Scholar 

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  1. Instituto de Informática, Universidade Federal do Rio Grande do Sul (UFRGS), Campus do Vale, Bloco IV, 15064, Porto Alegre, Brazil

    Débora Matos, Caroline Concatto & Luigi Carro

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  1. Débora Matos
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  2. Caroline Concatto
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  1. Campus do Vale - Bloco IV, Departamento de Informática Aplicada, Instituto de Informática, Av. Bento Gonçalves, 9500, Porte Alegre - RS, 91501-970, Brazil

    Antonio Carlos Schneider Beck

  2. Instituto de Informática da UFRGS, Av. Bento Gonçalves, 9500 - Campus do Vale - Bloco IV, Bairro Agronomia, 91501-970, Brazil

    Carlos Arthur Lang Lisbôa

  3. , Dept de Informática Aplicada, Instituto de Informática da UFRGS, Av. Bento Gonçalves, 9500 - Campus do Vale - Bloco IV, Bairro Agronomia, 91501-970, Brazil

    Luigi Carro

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Matos, D., Concatto, C., Carro, L. (2013). Reconfigurable Intercommunication Infrastructure: NoCs. In: Beck, A., Lang Lisbôa, C., Carro, L. (eds) Adaptable Embedded Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-1746-0_5

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