Abstract
A physical synthesis flow reads a mapped netlist produced by logic synthesis, then computes physical locations for gates and improves the performance of the circuit, until timing constraints are met. We observe that state-of-the-art flows consist of a series of optimizations that operate at two distinct scales, near-linear time algorithms that apply to the whole netlist, and more expensive transformations that typically operate on a handful of gates or interconnections.
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Papa, D.A., Markov, I.L. (2013). Conclusions. In: Multi-Objective Optimization in Physical Synthesis of Integrated Circuits. Lecture Notes in Electrical Engineering, vol 166. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-1356-1_10
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DOI: https://doi.org/10.1007/978-1-4614-1356-1_10
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